How pavan2415001/fpga-rle-image-compressor works
This is an FPGA image-compression system: an image is stored in FPGA memory, read and RLE-compressed plane by plane, then sent over UART for MATLAB reconstruction and PNG export. The README documents the color-design pipeline and a separate grayscale design; the tree identifies their RTL paths. No source excerpts were supplied, so internal blocks and wiring follow documented architecture rather than inspected RTL, and uncertain implementation details are omitted.
Main entry points: design_color_vivado.v Pixel reader · receiver.m MATLAB receiver · generate_image_mem.m Memory generator
Components 14
Image input
- Input image
- Memory generator
matlab/generate_image_mem.m - Image memory
rtl/color/design_color_vivado.v
FPGA compression
- Pixel reader
rtl/color/design_color_vivado.v - RGB plane control
rtl/color/design_color_vivado.v - RLE core
rtl/color/design_color_vivado.v - Packet formatter
rtl/color/design_color_vivado.v - Output FIFO
rtl/color/design_color_vivado.v
Serial transport
- UART transmitter
rtl/color/design_color_vivado.v - USB-UART bridge
Host reconstruction
- Host PC
- MATLAB receiver
matlab/receiver.m - Reconstructed image
Grayscale design
- Grayscale RTL design
rtl/grayscale/design_vivado.v
Connections 12
- Input image → Memory generator: provides image
- Memory generator → Image memory: prepares memory data
- Image memory → Pixel reader: supplies pixels
- RGB plane control → Pixel reader: selects color plane
- Pixel reader → RLE core: provides pixels
- RLE core → Packet formatter: emits runs
- Packet formatter → Output FIFO: writes packets
- Output FIFO → UART transmitter: supplies bytes
- UART transmitter → USB-UART bridge: transmits serial data
- USB-UART bridge → MATLAB receiver: delivers serial data
- Host PC → MATLAB receiver: runs
- MATLAB receiver → Reconstructed image: reconstructs and exports