How parsamohammadidev/risc-microarchitecture-in-verilog works
This repository provides three modular Verilog RISC processor implementations: single-cycle, multi-cycle, and pipelined, each based on a custom ISA. The README also identifies sample machine-code programs, datapath diagrams, and architecture documentation. The tree supports identifying RTL subsystems, but no source excerpts were provided, so internal calls and data paths cannot be verified. The ISA-to-processor links are documented; other subsystem relationships are left unspecified.
Main entry points: core/processor.v Processor core · core/processor.v Processor core · core/processor.v Processor core · single_cycle_isa.md ISA specification
Components 21
Single-cycle
- ISA specification
doc/single_cycle_isa.md - Processor core
src/single_cycle/rtl/core/processor.v - Control unit
src/single_cycle/rtl/core/control_unit.v - ALU and registers
src/single_cycle/rtl/components - Instruction and data memory
src/single_cycle/rtl/memory - Sample program
src/single_cycle/programs/program.hex
Multi-cycle
- ISA specification
doc/multi_cycle_isa.md - Processor core
src/multi_cycle/rtl/core/processor.v - Control unit
src/multi_cycle/rtl/core/control_unit.v - ALU and registers
src/multi_cycle/rtl/components - Instruction and data memory
src/multi_cycle/rtl/memory - Execution registers
src/multi_cycle/rtl/registers - Sample program
src/multi_cycle/programs/program.hex
Pipelined
- ISA specification
doc/pipelined_isa.md - Processor core
src/pipelined/rtl/core/processor.v - Control unit
src/pipelined/rtl/core/control_unit.v - Hazard and forwarding
src/pipelined/rtl/core - Pipeline registers
src/pipelined/rtl/pipeline - ALU and registers
src/pipelined/rtl/components - Instruction and data memory
src/pipelined/rtl/memory - Sample programs
src/pipelined/programs
Connections 3
- Processor core → ISA specification: implements
readme.md - Processor core → ISA specification: implements
readme.md - Processor core → ISA specification: implements
readme.md