# parsamohammadidev/risc-microarchitecture-in-verilog architecture

> Architecture diagram of the GitHub repository parsamohammadidev/risc-microarchitecture-in-verilog, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-11-09). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/parsamohammadidev/risc-microarchitecture-in-verilog
- Repository: https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog

## Overview

This repository provides three modular Verilog RISC processor implementations: single-cycle, multi-cycle, and pipelined, each based on a custom ISA. The README also identifies sample machine-code programs, datapath diagrams, and architecture documentation. The tree supports identifying RTL subsystems, but no source excerpts were provided, so internal calls and data paths cannot be verified. The ISA-to-processor links are documented; other subsystem relationships are left unspecified.

Main entry points: [`src/single_cycle/rtl/core/processor.v`](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/src/single_cycle/rtl/core/processor.v) (Processor core), [`src/multi_cycle/rtl/core/processor.v`](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/src/multi_cycle/rtl/core/processor.v) (Processor core), [`src/pipelined/rtl/core/processor.v`](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/src/pipelined/rtl/core/processor.v) (Processor core), [`doc/single_cycle_isa.md`](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/doc/single_cycle_isa.md) (ISA specification)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_single["Single-cycle"]
  node_single_isa["ISA specification"]
  node_single_cpu["Processor core<br/>[processor.v]"]
  node_single_control["Control unit<br/>[control_unit.v]"]
  node_single_components["ALU and registers"]
  node_single_memory[("Instruction and data memory")]
  node_single_program["Sample program<br/>[program.hex]"]
end

subgraph group_multi["Multi-cycle"]
  node_multi_isa["ISA specification<br/>[multi_cycle_isa.md]"]
  node_multi_cpu["Processor core<br/>[processor.v]"]
  node_multi_control["Control unit<br/>[control_unit.v]"]
  node_multi_components["ALU and registers"]
  node_multi_memory[("Instruction and data memory")]
  node_multi_state["Execution registers"]
  node_multi_program["Sample program<br/>[program.hex]"]
end

subgraph group_pipeline["Pipelined"]
  node_pipeline_isa["ISA specification<br/>[pipelined_isa.md]"]
  node_pipeline_cpu["Processor core<br/>[processor.v]"]
  node_pipeline_control["Control unit<br/>[control_unit.v]"]
  node_pipeline_hazards["Hazard and forwarding"]
  node_pipeline_stages["Pipeline registers"]
  node_pipeline_components["ALU and registers"]
  node_pipeline_memory[("Instruction and data memory")]
  node_pipeline_program["Sample programs"]
end

node_single_cpu -->|"implements"| node_single_isa
node_multi_cpu -->|"implements"| node_multi_isa
node_pipeline_cpu -->|"implements"| node_pipeline_isa

click node_single_isa "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/doc/single_cycle_isa.md"
click node_single_cpu "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/src/single_cycle/rtl/core/processor.v"
click node_single_control "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/src/single_cycle/rtl/core/control_unit.v"
click node_single_components "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/single_cycle/rtl/components"
click node_single_memory "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/single_cycle/rtl/memory"
click node_single_program "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/src/single_cycle/programs/program.hex"
click node_multi_isa "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/doc/multi_cycle_isa.md"
click node_multi_cpu "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/src/multi_cycle/rtl/core/processor.v"
click node_multi_control "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/src/multi_cycle/rtl/core/control_unit.v"
click node_multi_components "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/multi_cycle/rtl/components"
click node_multi_memory "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/multi_cycle/rtl/memory"
click node_multi_state "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/multi_cycle/rtl/registers"
click node_multi_program "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/src/multi_cycle/programs/program.hex"
click node_pipeline_isa "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/doc/pipelined_isa.md"
click node_pipeline_cpu "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/src/pipelined/rtl/core/processor.v"
click node_pipeline_control "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/src/pipelined/rtl/core/control_unit.v"
click node_pipeline_hazards "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/pipelined/rtl/core"
click node_pipeline_stages "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/pipelined/rtl/pipeline"
click node_pipeline_components "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/pipelined/rtl/components"
click node_pipeline_memory "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/pipelined/rtl/memory"
click node_pipeline_program "https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/pipelined/programs"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_single_isa,node_single_cpu,node_single_control,node_single_components,node_single_memory,node_single_program toneBlue
class node_multi_isa,node_multi_cpu,node_multi_control,node_multi_components,node_multi_memory,node_multi_state,node_multi_program toneAmber
class node_pipeline_isa,node_pipeline_cpu,node_pipeline_control,node_pipeline_hazards,node_pipeline_stages,node_pipeline_components,node_pipeline_memory,node_pipeline_program toneMint
```

## Components

### Single-cycle

- [ISA specification](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/doc/single_cycle_isa.md): `doc/single_cycle_isa.md`
- [Processor core](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/src/single_cycle/rtl/core/processor.v): `src/single_cycle/rtl/core/processor.v`
- [Control unit](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/src/single_cycle/rtl/core/control_unit.v): `src/single_cycle/rtl/core/control_unit.v`
- [ALU and registers](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/single_cycle/rtl/components): `src/single_cycle/rtl/components`
- [Instruction and data memory](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/single_cycle/rtl/memory): `src/single_cycle/rtl/memory`
- [Sample program](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/src/single_cycle/programs/program.hex): `src/single_cycle/programs/program.hex`

### Multi-cycle

- [ISA specification](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/doc/multi_cycle_isa.md): `doc/multi_cycle_isa.md`
- [Processor core](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/src/multi_cycle/rtl/core/processor.v): `src/multi_cycle/rtl/core/processor.v`
- [Control unit](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/src/multi_cycle/rtl/core/control_unit.v): `src/multi_cycle/rtl/core/control_unit.v`
- [ALU and registers](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/multi_cycle/rtl/components): `src/multi_cycle/rtl/components`
- [Instruction and data memory](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/multi_cycle/rtl/memory): `src/multi_cycle/rtl/memory`
- [Execution registers](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/multi_cycle/rtl/registers): `src/multi_cycle/rtl/registers`
- [Sample program](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/src/multi_cycle/programs/program.hex): `src/multi_cycle/programs/program.hex`

### Pipelined

- [ISA specification](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/doc/pipelined_isa.md): `doc/pipelined_isa.md`
- [Processor core](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/src/pipelined/rtl/core/processor.v): `src/pipelined/rtl/core/processor.v`
- [Control unit](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/blob/main/src/pipelined/rtl/core/control_unit.v): `src/pipelined/rtl/core/control_unit.v`
- [Hazard and forwarding](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/pipelined/rtl/core): `src/pipelined/rtl/core`
- [Pipeline registers](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/pipelined/rtl/pipeline): `src/pipelined/rtl/pipeline`
- [ALU and registers](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/pipelined/rtl/components): `src/pipelined/rtl/components`
- [Instruction and data memory](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/pipelined/rtl/memory): `src/pipelined/rtl/memory`
- [Sample programs](https://github.com/parsamohammadidev/risc-microarchitecture-in-verilog/tree/main/src/pipelined/programs): `src/pipelined/programs`

## Connections

- Processor core → ISA specification: implements (evidence: `readme.md`)
- Processor core → ISA specification: implements (evidence: `readme.md`)
- Processor core → ISA specification: implements (evidence: `readme.md`)