How ntu-alcomlab/lsv-pa works
The README identifies this as an NTU Logic Synthesis and Verification course repository forked from ABC; its stated PA1 concerns cut enumeration and truth-table/BDD generation. The supplied tree, however, is predominantly ABC’s general-purpose logic synthesis and verification runtime and does not include the referenced assignment directory. The graph therefore summarizes the visible ABC product and its major capabilities. Paths and subsystem boundaries are tree-supported; sampled excerpts do not establish most runtime call wiring, so the graph avoids speculative internal edges.
Main entry points: cmd.c Command shell · abcNtk.c Logic network · abcVerify.c Formal commands · main.c ABC executable
Components 17
User Interface
- ABC executable
src/base/main/main.c - Command shell
src/base/cmd/cmd.c - Circuit formats
src/base/io/io.c - Circuit output
src/base/io/ioWriteVerilog.c
Circuit Models
- Logic network
src/base/abc/abcNtk.c - AIG operations
src/aig/aig/aigMan.c - GIA operations
src/aig/gia/giaMan.c - Cut enumeration
src/map/if/ifCut.c - BDD operations
src/bdd/cudd/cuddAPI.c
Synthesis
- Logic rewriting
src/base/abci/abcRewrite.c - Resubstitution
src/base/abci/abcOrchestration.c - Technology mapping
src/map/if/ifMap.c - PLA minimization
src/misc/espresso/main.c
Verification
- SAT solving
src/sat/msat/msatSolverSearch.c - Sequential analysis
src/aig/saig/saig.h - Formal commands
src/base/abci/abcVerify.c
Other components
- Engineer
Connections 16
- Engineer → ABC executable: invokes
- ABC executable → Command shell: starts
- Command shell → Circuit formats: dispatches
- Circuit formats → Logic network: reads circuits
- Command shell → Logic rewriting: dispatches
- Command shell → Resubstitution: dispatches
- Command shell → Technology mapping: dispatches
- Command shell → PLA minimization: dispatches
- Command shell → Formal commands: dispatches
- Logic network → AIG operations: represented as
- Logic network → GIA operations: represented as
- Command shell → Cut enumeration: dispatches
- Command shell → BDD operations: dispatches
- Formal commands → SAT solving: uses
- Formal commands → Sequential analysis: analyzes
- Logic network → Circuit output: written as