# ntu-alcomlab/lsv-pa architecture

> Architecture diagram of the GitHub repository ntu-alcomlab/lsv-pa, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-29). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/ntu-alcomlab/lsv-pa
- Repository: https://github.com/ntu-alcomlab/lsv-pa

## Overview

The README identifies this as an NTU Logic Synthesis and Verification course repository forked from ABC; its stated PA1 concerns cut enumeration and truth-table/BDD generation. The supplied tree, however, is predominantly ABC’s general-purpose logic synthesis and verification runtime and does not include the referenced assignment directory. The graph therefore summarizes the visible ABC product and its major capabilities. Paths and subsystem boundaries are tree-supported; sampled excerpts do not establish most runtime call wiring, so the graph avoids speculative internal edges.

Main entry points: [`src/base/cmd/cmd.c`](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/cmd/cmd.c) (Command shell), [`src/base/abc/abcNtk.c`](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/abc/abcNtk.c) (Logic network), [`src/base/abci/abcVerify.c`](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/abci/abcVerify.c) (Formal commands), [`src/base/main/main.c`](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/main/main.c) (ABC executable)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_interface["User Interface"]
  node_abc_cli["ABC executable<br/>[main.c]"]
  node_command_shell["Command shell<br/>[cmd.c]"]
  node_io_formats["Circuit formats<br/>[io.c]"]
  node_output_formats["Circuit output<br/>[ioWriteVerilog.c]"]
end

subgraph group_circuits["Circuit Models"]
  node_network["Logic network<br/>[abcNtk.c]"]
  node_aig["AIG operations<br/>[aigMan.c]"]
  node_gia["GIA operations<br/>[giaMan.c]"]
  node_cuts["Cut enumeration<br/>[ifCut.c]"]
  node_bdd["BDD operations<br/>[cuddAPI.c]"]
end

subgraph group_synthesis["Synthesis"]
  node_rewrite["Logic rewriting<br/>[abcRewrite.c]"]
  node_resub["Resubstitution<br/>[abcOrchestration.c]"]
  node_technology_map["Technology mapping<br/>[ifMap.c]"]
  node_espresso["PLA minimization<br/>[main.c]"]
end

subgraph group_verification["Verification"]
  node_sat["SAT solving<br/>[msatSolverSearch.c]"]
  node_sequential["Sequential analysis<br/>[saig.h]"]
  node_formal["Formal commands<br/>[abcVerify.c]"]
end

node_engineer(("Engineer"))

node_engineer -->|"invokes"| node_abc_cli
node_abc_cli -->|"starts"| node_command_shell
node_command_shell -->|"dispatches"| node_io_formats
node_io_formats -->|"reads circuits"| node_network
node_command_shell -->|"dispatches"| node_rewrite
node_command_shell -->|"dispatches"| node_resub
node_command_shell -->|"dispatches"| node_technology_map
node_command_shell -->|"dispatches"| node_espresso
node_command_shell -->|"dispatches"| node_formal
node_network -->|"represented as"| node_aig
node_network -->|"represented as"| node_gia
node_command_shell -->|"dispatches"| node_cuts
node_command_shell -->|"dispatches"| node_bdd
node_formal -->|"uses"| node_sat
node_formal -->|"analyzes"| node_sequential
node_network -->|"written as"| node_output_formats

click node_abc_cli "https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/main/main.c"
click node_command_shell "https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/cmd/cmd.c"
click node_io_formats "https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/io/io.c"
click node_network "https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/abc/abcNtk.c"
click node_aig "https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/aig/aig/aigMan.c"
click node_gia "https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/aig/gia/giaMan.c"
click node_cuts "https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/map/if/ifCut.c"
click node_bdd "https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/bdd/cudd/cuddAPI.c"
click node_rewrite "https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/abci/abcRewrite.c"
click node_resub "https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/abci/abcOrchestration.c"
click node_technology_map "https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/map/if/ifMap.c"
click node_espresso "https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/misc/espresso/main.c"
click node_sat "https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/sat/msat/msatSolverSearch.c"
click node_sequential "https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/aig/saig/saig.h"
click node_formal "https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/abci/abcVerify.c"
click node_output_formats "https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/io/ioWriteVerilog.c"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_abc_cli,node_command_shell,node_io_formats,node_output_formats toneBlue
class node_network,node_aig,node_gia,node_cuts,node_bdd toneAmber
class node_rewrite,node_resub,node_technology_map,node_espresso toneMint
class node_sat,node_sequential,node_formal toneRose
class node_engineer toneIndigo
```

## Components

### User Interface

- [ABC executable](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/main/main.c): `src/base/main/main.c`
- [Command shell](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/cmd/cmd.c): `src/base/cmd/cmd.c`
- [Circuit formats](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/io/io.c): `src/base/io/io.c`
- [Circuit output](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/io/ioWriteVerilog.c): `src/base/io/ioWriteVerilog.c`

### Circuit Models

- [Logic network](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/abc/abcNtk.c): `src/base/abc/abcNtk.c`
- [AIG operations](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/aig/aig/aigMan.c): `src/aig/aig/aigMan.c`
- [GIA operations](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/aig/gia/giaMan.c): `src/aig/gia/giaMan.c`
- [Cut enumeration](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/map/if/ifCut.c): `src/map/if/ifCut.c`
- [BDD operations](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/bdd/cudd/cuddAPI.c): `src/bdd/cudd/cuddAPI.c`

### Synthesis

- [Logic rewriting](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/abci/abcRewrite.c): `src/base/abci/abcRewrite.c`
- [Resubstitution](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/abci/abcOrchestration.c): `src/base/abci/abcOrchestration.c`
- [Technology mapping](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/map/if/ifMap.c): `src/map/if/ifMap.c`
- [PLA minimization](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/misc/espresso/main.c): `src/misc/espresso/main.c`

### Verification

- [SAT solving](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/sat/msat/msatSolverSearch.c): `src/sat/msat/msatSolverSearch.c`
- [Sequential analysis](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/aig/saig/saig.h): `src/aig/saig/saig.h`
- [Formal commands](https://github.com/ntu-alcomlab/lsv-pa/blob/master/src/base/abci/abcVerify.c): `src/base/abci/abcVerify.c`

### Other components

- **Engineer**

## Connections

- Engineer → ABC executable: invokes
- ABC executable → Command shell: starts
- Command shell → Circuit formats: dispatches
- Circuit formats → Logic network: reads circuits
- Command shell → Logic rewriting: dispatches
- Command shell → Resubstitution: dispatches
- Command shell → Technology mapping: dispatches
- Command shell → PLA minimization: dispatches
- Command shell → Formal commands: dispatches
- Logic network → AIG operations: represented as
- Logic network → GIA operations: represented as
- Command shell → Cut enumeration: dispatches
- Command shell → BDD operations: dispatches
- Formal commands → SAT solving: uses
- Formal commands → Sequential analysis: analyzes
- Logic network → Circuit output: written as