How nguyenquanicd/vlsit_rtl_generator_ai_model works
VLSIT is a Claude Code prompt-driven flow for AI-assisted RTL design and verification, not a standalone workflow engine. Its principal workflow moves a design description through specification, requirements, and configuration into RTL and verification artifacts, then produces reviewable evidence and documentation. RTL and testbench generation can proceed independently from the approved configuration; assertions connect to RTL, while verification uses the testbench and traceability artifacts. The README documents these relationships; individual prompt implementations were not sampled, so finer-grained internal wiring is omitted.
Main entry points: verification.md Verification prompt · rtl_generator.md RTL generator · spec_writer.md Spec writer · spec_pdf_generator.md Specification PDF generator
Components 21
Flow orchestration
- Autoflow prompt
.claude/commands/autoflow.md
Specification and configuration
- Spec writer
.claude/commands/spec_writer.md - Hardware specification
- Spec parser
.claude/commands/spec_parser.md - Structured requirements
- Configuration UI
.claude/commands/config_ui.md - Final configuration
RTL and properties
- RTL generator
.claude/commands/rtl_generator.md - SystemVerilog RTL
- SVA generator
.claude/commands/sva_generator.md - Assertions and bind
Verification and traceability
- Testbench generator
.claude/commands/tb_generator.md - Testbench and plan
- Verification prompt
.claude/commands/verification.md - Requirement traceability matrix
- Verification report
Documentation
- Specification PDF generator
.claude/commands/spec_pdf_generator.md - Specification documentation
Other components
- Design engineer
- Lint and synthesis tools
- Simulation tools
Connections 24
- Design engineer → Autoflow prompt: starts flow
- Design engineer → Spec writer: provides description
- Autoflow prompt → Spec writer: coordinates
- Spec writer → Hardware specification: writes
- Hardware specification → Spec parser: parses
- Spec parser → Structured requirements: extracts requirements
- Structured requirements → Configuration UI: informs choices
- Configuration UI → Final configuration: produces
- Final configuration → RTL generator: configures
- Final configuration → Testbench generator: configures
- RTL generator → SystemVerilog RTL: generates
- RTL generator → Lint and synthesis tools: runs lint and synthesis
- SystemVerilog RTL → SVA generator: provides RTL
- SVA generator → Assertions and bind: generates properties
- Testbench generator → Testbench and plan: generates tests
- Assertions and bind → Verification prompt: supplies properties
- Testbench and plan → Verification prompt: supplies tests
- Verification prompt → Simulation tools: runs verification
- Verification prompt → Requirement traceability matrix: updates traceability
- Verification prompt → Verification report: produces results
- Structured requirements → Requirement traceability matrix: traces requirements
- SystemVerilog RTL → Specification PDF generator: informs documentation
- Verification report → Specification PDF generator: informs documentation
- Specification PDF generator → Specification documentation: generates