# nguyenquanicd/vlsit_rtl_generator_ai_model architecture

> Architecture diagram of the GitHub repository nguyenquanicd/vlsit_rtl_generator_ai_model, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-26). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/nguyenquanicd/vlsit_rtl_generator_ai_model
- Repository: https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model

## Overview

VLSIT is a Claude Code prompt-driven flow for AI-assisted RTL design and verification, not a standalone workflow engine. Its principal workflow moves a design description through specification, requirements, and configuration into RTL and verification artifacts, then produces reviewable evidence and documentation. RTL and testbench generation can proceed independently from the approved configuration; assertions connect to RTL, while verification uses the testbench and traceability artifacts. The README documents these relationships; individual prompt implementations were not sampled, so finer-grained internal wiring is omitted.

Main entry points: [`.claude/commands/verification.md`](https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/verification.md) (Verification prompt), [`.claude/commands/rtl_generator.md`](https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/rtl_generator.md) (RTL generator), [`.claude/commands/spec_writer.md`](https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/spec_writer.md) (Spec writer), [`.claude/commands/spec_pdf_generator.md`](https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/spec_pdf_generator.md) (Specification PDF generator)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_orchestration["Flow orchestration"]
  node_autoflow["Autoflow prompt<br/>[autoflow.md]"]
end

subgraph group_spec_config["Specification and configuration"]
  node_writer["Spec writer<br/>[spec_writer.md]"]
  node_spec["Hardware specification"]
  node_parser["Spec parser<br/>[spec_parser.md]"]
  node_requirements["Structured requirements"]
  node_config["Configuration UI<br/>[config_ui.md]"]
  node_final_config["Final configuration"]
end

subgraph group_design["RTL and properties"]
  node_rtlgen["RTL generator<br/>[rtl_generator.md]"]
  node_rtl["SystemVerilog RTL"]
  node_svagen["SVA generator<br/>[sva_generator.md]"]
  node_assertions["Assertions and bind"]
end

subgraph group_verification["Verification and traceability"]
  node_tbgen["Testbench generator<br/>[tb_generator.md]"]
  node_testbench["Testbench and plan"]
  node_verifier["Verification prompt<br/>[verification.md]"]
  node_rtm["Requirement traceability matrix"]
  node_report["Verification report"]
end

subgraph group_reporting["Documentation"]
  node_pdfgen["Specification PDF generator"]
  node_docs["Specification documentation"]
end

node_designer(("Design engineer"))
node_eda["Lint and synthesis tools"]
node_simtools["Simulation tools"]

node_designer -->|"starts flow"| node_autoflow
node_designer -->|"provides description"| node_writer
node_autoflow -->|"coordinates"| node_writer
node_writer -->|"writes"| node_spec
node_spec -->|"parses"| node_parser
node_parser -->|"extracts requirements"| node_requirements
node_requirements -->|"informs choices"| node_config
node_config -->|"produces"| node_final_config
node_final_config -->|"configures"| node_rtlgen
node_final_config -->|"configures"| node_tbgen
node_rtlgen -->|"generates"| node_rtl
node_rtlgen -->|"runs lint and synthesis"| node_eda
node_rtl -->|"provides RTL"| node_svagen
node_svagen -->|"generates properties"| node_assertions
node_tbgen -->|"generates tests"| node_testbench
node_assertions -->|"supplies properties"| node_verifier
node_testbench -->|"supplies tests"| node_verifier
node_verifier -->|"runs verification"| node_simtools
node_verifier -->|"updates traceability"| node_rtm
node_verifier -->|"produces results"| node_report
node_requirements -->|"traces requirements"| node_rtm
node_rtl -->|"informs documentation"| node_pdfgen
node_report -->|"informs documentation"| node_pdfgen
node_pdfgen -->|"generates"| node_docs

click node_autoflow "https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/autoflow.md"
click node_writer "https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/spec_writer.md"
click node_parser "https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/spec_parser.md"
click node_config "https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/config_ui.md"
click node_rtlgen "https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/rtl_generator.md"
click node_svagen "https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/sva_generator.md"
click node_tbgen "https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/tb_generator.md"
click node_verifier "https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/verification.md"
click node_pdfgen "https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/spec_pdf_generator.md"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_autoflow toneBlue
class node_writer,node_spec,node_parser,node_requirements,node_config,node_final_config toneAmber
class node_rtlgen,node_rtl,node_svagen,node_assertions toneMint
class node_tbgen,node_testbench,node_verifier,node_rtm,node_report toneRose
class node_pdfgen,node_docs,node_designer,node_eda,node_simtools toneIndigo
```

## Components

### Flow orchestration

- [Autoflow prompt](https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/autoflow.md): `.claude/commands/autoflow.md`

### Specification and configuration

- [Spec writer](https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/spec_writer.md): `.claude/commands/spec_writer.md`
- **Hardware specification**
- [Spec parser](https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/spec_parser.md): `.claude/commands/spec_parser.md`
- **Structured requirements**
- [Configuration UI](https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/config_ui.md): `.claude/commands/config_ui.md`
- **Final configuration**

### RTL and properties

- [RTL generator](https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/rtl_generator.md): `.claude/commands/rtl_generator.md`
- **SystemVerilog RTL**
- [SVA generator](https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/sva_generator.md): `.claude/commands/sva_generator.md`
- **Assertions and bind**

### Verification and traceability

- [Testbench generator](https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/tb_generator.md): `.claude/commands/tb_generator.md`
- **Testbench and plan**
- [Verification prompt](https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/verification.md): `.claude/commands/verification.md`
- **Requirement traceability matrix**
- **Verification report**

### Documentation

- [Specification PDF generator](https://github.com/nguyenquanicd/vlsit_rtl_generator_ai_model/blob/main/.claude/commands/spec_pdf_generator.md): `.claude/commands/spec_pdf_generator.md`
- **Specification documentation**

### Other components

- **Design engineer**
- **Lint and synthesis tools**
- **Simulation tools**

## Connections

- Design engineer → Autoflow prompt: starts flow
- Design engineer → Spec writer: provides description
- Autoflow prompt → Spec writer: coordinates
- Spec writer → Hardware specification: writes
- Hardware specification → Spec parser: parses
- Spec parser → Structured requirements: extracts requirements
- Structured requirements → Configuration UI: informs choices
- Configuration UI → Final configuration: produces
- Final configuration → RTL generator: configures
- Final configuration → Testbench generator: configures
- RTL generator → SystemVerilog RTL: generates
- RTL generator → Lint and synthesis tools: runs lint and synthesis
- SystemVerilog RTL → SVA generator: provides RTL
- SVA generator → Assertions and bind: generates properties
- Testbench generator → Testbench and plan: generates tests
- Assertions and bind → Verification prompt: supplies properties
- Testbench and plan → Verification prompt: supplies tests
- Verification prompt → Simulation tools: runs verification
- Verification prompt → Requirement traceability matrix: updates traceability
- Verification prompt → Verification report: produces results
- Structured requirements → Requirement traceability matrix: traces requirements
- SystemVerilog RTL → Specification PDF generator: informs documentation
- Verification report → Specification PDF generator: informs documentation
- Specification PDF generator → Specification documentation: generates