How mrbear2-rus/sigflow_fpga works
SigFlow is a desktop FPGA design environment. Its apparent user workflow is to edit a project’s Verilog, run FPGA implementation or simulation, then inspect reports and waveforms; the tree also shows hardware debug, device programming, and plugin capabilities. The sampled simulation code confirms orchestration of Verilator and job/process support, and the trace-query excerpt confirms asynchronous queries against a trace source. Most other wiring is inferred from module names, so uncertain call relationships are omitted.
Main entry points: FpgaSynthesisJob.cpp Synthesis job · MainFrame.cpp Main window · SimulationEngine.cpp Simulation engine · VerilogManager.cpp Verilog editor
Components 24
Project and editing
- Main window
main/MainFrame.cpp - Project tree
main/ProjectTreePanel.cpp - Verilog editor
main/VerilogManager.cpp - Signal-flow editor
main/SigFlowTreePanel.cpp
FPGA implementation
- Synthesis job
main/FpgaSynthesisJob.cpp - Yosys synthesis
InnerPlugin/eda-synth-yosys/src/YosysSynthesizer.cpp - Gowin packing
InnerPlugin/eda-pack-gowin/src/GowinPacker.cpp - Placement routing
InnerPlugin/eda-pnr-nextpnr/src/NextpnrPlaceRouter.cpp - Constraint validation
InnerPlugin/eda-cst-gowin-cst/src/CstFileValidator.cpp - Target profiles
InnerPlugin/eda-target-tangnano9k/src/TargetProfileStore.cpp - FPGA programmer
InnerPlugin/eda-program-openfpgaloader/src/OpenFpgaLoaderProgrammer.cpp
Simulation and waveforms
- Simulation engine
main/Simulation/SimulationEngine.cpp - Verilator simulator
InnerPlugin/eda-sim-verilator/src/VerilatorSimulator.cpp - VCD backend
InnerPlugin/eda-wave-vcd/src/VcdWaveformBackend.cpp - Trace query service
main/trace/TraceQueryService.cpp - Waveform view
main/wave/WaveformView.cpp
Hardware debug
- Debug session
main/debug/DebugSession.cpp - Debug acquisition
main/debug/DebugAcquisition.cpp - Device transports
main/debug/ITransport.h
Runtime and plugins
- Plugin manager
main/PluginManager.cpp - Job service
main/jobs/JobService.cpp
Other components
- Designer
- Verilator
- FPGA hardware
Connections 23
- Designer → Main window: uses
- Main window → Project tree: presents
- Main window → Verilog editor: hosts editing
- Main window → Signal-flow editor: hosts editing
- Verilog editor → Synthesis job: starts synthesis
- Synthesis job → Yosys synthesis: runs synthesis
- Synthesis job → Gowin packing: runs packing
- Synthesis job → Placement routing: runs routing
- Synthesis job → Constraint validation: validates constraints
- Synthesis job → Target profiles: uses profile
- FPGA programmer → FPGA hardware: programs
- Verilog editor → Simulation engine: starts simulation
- Simulation engine → Verilator simulator: runs simulation
- Simulation engine → Job service: registers jobs
- Simulation engine → Verilator: executes
- Verilator simulator → VCD backend: produces waveform
- Waveform view → Trace query service: requests transitions
- Trace query service → VCD backend: queries trace
- Designer → Debug session: starts debug
- Debug session → Debug acquisition: requests capture
- Debug acquisition → Device transports: uses transport
- Device transports → FPGA hardware: communicates
- Main window → Plugin manager: loads plugins