# mrbear2-rus/sigflow_fpga architecture

> Architecture diagram of the GitHub repository mrbear2-rus/sigflow_fpga, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-28). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/mrbear2-rus/sigflow_fpga
- Repository: https://github.com/mrbear2-rus/sigflow_fpga

## Overview

SigFlow is a desktop FPGA design environment. Its apparent user workflow is to edit a project’s Verilog, run FPGA implementation or simulation, then inspect reports and waveforms; the tree also shows hardware debug, device programming, and plugin capabilities. The sampled simulation code confirms orchestration of Verilator and job/process support, and the trace-query excerpt confirms asynchronous queries against a trace source. Most other wiring is inferred from module names, so uncertain call relationships are omitted.

Main entry points: [`main/FpgaSynthesisJob.cpp`](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/FpgaSynthesisJob.cpp) (Synthesis job), [`main/MainFrame.cpp`](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/MainFrame.cpp) (Main window), [`main/Simulation/SimulationEngine.cpp`](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/Simulation/SimulationEngine.cpp) (Simulation engine), [`main/VerilogManager.cpp`](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/VerilogManager.cpp) (Verilog editor)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_ui["Project and editing"]
  node_mainframe["Main window<br/>[MainFrame.cpp]"]
  node_projecttree["Project tree"]
  node_verilog["Verilog editor<br/>[VerilogManager.cpp]"]
  node_sigflowtree["Signal-flow editor"]
end

subgraph group_fpga["FPGA implementation"]
  node_synthjob["Synthesis job"]
  node_yosys["Yosys synthesis"]
  node_packer["Gowin packing<br/>[GowinPacker.cpp]"]
  node_pnr["Placement routing"]
  node_constraints["Constraint validation"]
  node_target[("Target profiles")]
  node_programmer["FPGA programmer"]
end

subgraph group_simwave["Simulation and waveforms"]
  node_simengine["Simulation engine"]
  node_simplugin["Verilator simulator"]
  node_vcd["VCD backend"]
  node_query["Trace query service"]
  node_waveview["Waveform view<br/>[WaveformView.cpp]"]
end

subgraph group_debug["Hardware debug"]
  node_debugsession["Debug session<br/>[DebugSession.cpp]"]
  node_acquisition["Debug acquisition"]
  node_transport["Device transports<br/>[ITransport.h]"]
end

subgraph group_runtime["Runtime and plugins"]
  node_pluginmanager["Plugin manager<br/>[PluginManager.cpp]"]
  node_jobservice["Job service<br/>[JobService.cpp]"]
end

node_designer(("Designer"))
node_verilator_tool["Verilator"]
node_hardware["FPGA hardware"]

node_designer -->|"uses"| node_mainframe
node_mainframe -->|"presents"| node_projecttree
node_mainframe -->|"hosts editing"| node_verilog
node_mainframe -->|"hosts editing"| node_sigflowtree
node_verilog -->|"starts synthesis"| node_synthjob
node_synthjob -->|"runs synthesis"| node_yosys
node_synthjob -->|"runs packing"| node_packer
node_synthjob -->|"runs routing"| node_pnr
node_synthjob -->|"validates constraints"| node_constraints
node_synthjob -->|"uses profile"| node_target
node_programmer -->|"programs"| node_hardware
node_verilog -->|"starts simulation"| node_simengine
node_simengine -.->|"runs simulation"| node_simplugin
node_simengine -->|"registers jobs"| node_jobservice
node_simengine -->|"executes"| node_verilator_tool
node_simplugin -.->|"produces waveform"| node_vcd
node_waveview -->|"requests transitions"| node_query
node_query -.->|"queries trace"| node_vcd
node_designer -->|"starts debug"| node_debugsession
node_debugsession -->|"requests capture"| node_acquisition
node_acquisition -->|"uses transport"| node_transport
node_transport -->|"communicates"| node_hardware
node_mainframe -->|"loads plugins"| node_pluginmanager

click node_mainframe "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/MainFrame.cpp"
click node_projecttree "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/ProjectTreePanel.cpp"
click node_verilog "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/VerilogManager.cpp"
click node_sigflowtree "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/SigFlowTreePanel.cpp"
click node_synthjob "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/FpgaSynthesisJob.cpp"
click node_yosys "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/InnerPlugin/eda-synth-yosys/src/YosysSynthesizer.cpp"
click node_packer "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/InnerPlugin/eda-pack-gowin/src/GowinPacker.cpp"
click node_pnr "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/InnerPlugin/eda-pnr-nextpnr/src/NextpnrPlaceRouter.cpp"
click node_constraints "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/InnerPlugin/eda-cst-gowin-cst/src/CstFileValidator.cpp"
click node_target "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/InnerPlugin/eda-target-tangnano9k/src/TargetProfileStore.cpp"
click node_programmer "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/InnerPlugin/eda-program-openfpgaloader/src/OpenFpgaLoaderProgrammer.cpp"
click node_simengine "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/Simulation/SimulationEngine.cpp"
click node_simplugin "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/InnerPlugin/eda-sim-verilator/src/VerilatorSimulator.cpp"
click node_vcd "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/InnerPlugin/eda-wave-vcd/src/VcdWaveformBackend.cpp"
click node_query "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/trace/TraceQueryService.cpp"
click node_waveview "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/wave/WaveformView.cpp"
click node_debugsession "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/debug/DebugSession.cpp"
click node_acquisition "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/debug/DebugAcquisition.cpp"
click node_transport "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/debug/ITransport.h"
click node_pluginmanager "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/PluginManager.cpp"
click node_jobservice "https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/jobs/JobService.cpp"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_mainframe,node_projecttree,node_verilog,node_sigflowtree toneBlue
class node_synthjob,node_yosys,node_packer,node_pnr,node_constraints,node_target,node_programmer toneAmber
class node_simengine,node_simplugin,node_vcd,node_query,node_waveview toneMint
class node_debugsession,node_acquisition,node_transport toneRose
class node_pluginmanager,node_jobservice,node_designer,node_verilator_tool,node_hardware toneIndigo
```

## Components

### Project and editing

- [Main window](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/MainFrame.cpp): `main/MainFrame.cpp`
- [Project tree](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/ProjectTreePanel.cpp): `main/ProjectTreePanel.cpp`
- [Verilog editor](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/VerilogManager.cpp): `main/VerilogManager.cpp`
- [Signal-flow editor](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/SigFlowTreePanel.cpp): `main/SigFlowTreePanel.cpp`

### FPGA implementation

- [Synthesis job](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/FpgaSynthesisJob.cpp): `main/FpgaSynthesisJob.cpp`
- [Yosys synthesis](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/InnerPlugin/eda-synth-yosys/src/YosysSynthesizer.cpp): `InnerPlugin/eda-synth-yosys/src/YosysSynthesizer.cpp`
- [Gowin packing](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/InnerPlugin/eda-pack-gowin/src/GowinPacker.cpp): `InnerPlugin/eda-pack-gowin/src/GowinPacker.cpp`
- [Placement routing](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/InnerPlugin/eda-pnr-nextpnr/src/NextpnrPlaceRouter.cpp): `InnerPlugin/eda-pnr-nextpnr/src/NextpnrPlaceRouter.cpp`
- [Constraint validation](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/InnerPlugin/eda-cst-gowin-cst/src/CstFileValidator.cpp): `InnerPlugin/eda-cst-gowin-cst/src/CstFileValidator.cpp`
- [Target profiles](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/InnerPlugin/eda-target-tangnano9k/src/TargetProfileStore.cpp): `InnerPlugin/eda-target-tangnano9k/src/TargetProfileStore.cpp`
- [FPGA programmer](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/InnerPlugin/eda-program-openfpgaloader/src/OpenFpgaLoaderProgrammer.cpp): `InnerPlugin/eda-program-openfpgaloader/src/OpenFpgaLoaderProgrammer.cpp`

### Simulation and waveforms

- [Simulation engine](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/Simulation/SimulationEngine.cpp): `main/Simulation/SimulationEngine.cpp`
- [Verilator simulator](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/InnerPlugin/eda-sim-verilator/src/VerilatorSimulator.cpp): `InnerPlugin/eda-sim-verilator/src/VerilatorSimulator.cpp`
- [VCD backend](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/InnerPlugin/eda-wave-vcd/src/VcdWaveformBackend.cpp): `InnerPlugin/eda-wave-vcd/src/VcdWaveformBackend.cpp`
- [Trace query service](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/trace/TraceQueryService.cpp): `main/trace/TraceQueryService.cpp`
- [Waveform view](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/wave/WaveformView.cpp): `main/wave/WaveformView.cpp`

### Hardware debug

- [Debug session](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/debug/DebugSession.cpp): `main/debug/DebugSession.cpp`
- [Debug acquisition](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/debug/DebugAcquisition.cpp): `main/debug/DebugAcquisition.cpp`
- [Device transports](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/debug/ITransport.h): `main/debug/ITransport.h`

### Runtime and plugins

- [Plugin manager](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/PluginManager.cpp): `main/PluginManager.cpp`
- [Job service](https://github.com/mrbear2-rus/sigflow_fpga/blob/SigFlow_FPGA_CMake/main/jobs/JobService.cpp): `main/jobs/JobService.cpp`

### Other components

- **Designer**
- **Verilator**
- **FPGA hardware**

## Connections

- Designer → Main window: uses
- Main window → Project tree: presents
- Main window → Verilog editor: hosts editing
- Main window → Signal-flow editor: hosts editing
- Verilog editor → Synthesis job: starts synthesis
- Synthesis job → Yosys synthesis: runs synthesis
- Synthesis job → Gowin packing: runs packing
- Synthesis job → Placement routing: runs routing
- Synthesis job → Constraint validation: validates constraints
- Synthesis job → Target profiles: uses profile
- FPGA programmer → FPGA hardware: programs
- Verilog editor → Simulation engine: starts simulation
- Simulation engine → Verilator simulator: runs simulation
- Simulation engine → Job service: registers jobs
- Simulation engine → Verilator: executes
- Verilator simulator → VCD backend: produces waveform
- Waveform view → Trace query service: requests transitions
- Trace query service → VCD backend: queries trace
- Designer → Debug session: starts debug
- Debug session → Debug acquisition: requests capture
- Debug acquisition → Device transports: uses transport
- Device transports → FPGA hardware: communicates
- Main window → Plugin manager: loads plugins