How mivonsim/mivon works
Mivon is a SystemVerilog RTL simulator: users submit source files and options through the CLI or GUI, which drive compilation, elaboration, simulation, and waveform/report output. The documented pipeline establishes the principal stage order; sampled source additionally supports incremental compilation, GUI workflow, and co-simulation. The tree and README identify synthesis, formal verification, emulation, and verification tooling as separate capabilities, but their detailed wiring is not established by the excerpts, so they are shown as independent branches rather than an assumed pipeline.
Main entry points: mod.rs Simulation Engine · compile_session.rs Compile Session · main.rs CLI Runner · app.rs GUI App
Components 24
User Interfaces
- CLI Runner
src/main.rs - GUI App
crates/mivon-gui/src/app.rs
Compile Pipeline
- Preprocessor
crates/mivon-parser/src/preprocessor.rs - Lexer
crates/mivon-parser/src/lexer.rs - Parser
crates/mivon-parser/src/lib.rs - AST
crates/mivon-ast/src/lib.rs - Elaborator
crates/mivon-elaboration/src/lib.rs - Compile Session
crates/mivon-compiler/src/frontend/compile_session.rs - Incremental Cache
crates/mivon-compiler/src/micd/cache/pipeline.rs - Simulation IR
crates/mivon-ir/src/ir.rs
Simulation
- Simulation Engine
crates/mivon-simulator/src/simulator/engine/mod.rs - Event Scheduler
crates/mivon-simulator/src/simulator/engine/scheduler/mod.rs - UVM Runtime
crates/mivon-simulator/src/simulator/engine/uvm/mod.rs - Co-simulation Server
crates/mivon-simulator/src/simulator/cosim/server.rs
Verification Outputs
- Coverage Database
crates/mivon-simulator/src/simulator/coverage_db.rs - Waveform Writers
crates/mivon-simulator/src/waveform/mod.rs
Additional Capabilities
- Synthesis
crates/mivon-synth/src/lib.rs - Formal Verification
crates/mivon-formal/src/lib.rs - CPU Emulator
crates/mivon-emu/src/lib.rs - Fuzz Testing
crates/mivon-fuzz/src/lib.rs
Other components
- RTL User
- SystemVerilog
- External Simulator
- VCD / FST
Connections 26
- RTL User → CLI Runner: invokes
- RTL User → GUI App: uses
- RTL User → SystemVerilog: provides
- CLI Runner → SystemVerilog: loads
- CLI Runner → Compile Session: starts compile
- GUI App → Compile Session: compiles project
- Compile Session → Preprocessor: preprocesses
- Preprocessor → Lexer: passes source
- Lexer → Parser: passes tokens
- Parser → AST: produces AST
- AST → Elaborator: elaborates
- Elaborator → Simulation IR: lowers
- Compile Session → Incremental Cache: populates
- Compile Session → Simulation Engine: starts simulation
- Simulation IR → Simulation Engine: design input
- Simulation Engine → Event Scheduler: dispatches events
- Simulation Engine → UVM Runtime: executes UVM
- Simulation Engine → Coverage Database: records coverage
- Simulation Engine → Waveform Writers: records signals
- Waveform Writers → VCD / FST: writes
- External Simulator → Co-simulation Server: connects
- Co-simulation Server → Simulation Engine: exchanges signals
- RTL User → Synthesis: requests synthesis
- RTL User → Formal Verification: requests verification
- RTL User → CPU Emulator: runs emulation
- RTL User → Fuzz Testing: runs fuzzing