# mivonsim/mivon architecture

> Architecture diagram of the GitHub repository mivonsim/mivon, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-28). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/mivonsim/mivon
- Repository: https://github.com/mivonsim/mivon

## Overview

Mivon is a SystemVerilog RTL simulator: users submit source files and options through the CLI or GUI, which drive compilation, elaboration, simulation, and waveform/report output. The documented pipeline establishes the principal stage order; sampled source additionally supports incremental compilation, GUI workflow, and co-simulation. The tree and README identify synthesis, formal verification, emulation, and verification tooling as separate capabilities, but their detailed wiring is not established by the excerpts, so they are shown as independent branches rather than an assumed pipeline.

Main entry points: [`crates/mivon-simulator/src/simulator/engine/mod.rs`](https://github.com/mivonsim/mivon/blob/main/crates/mivon-simulator/src/simulator/engine/mod.rs) (Simulation Engine), [`crates/mivon-compiler/src/frontend/compile_session.rs`](https://github.com/mivonsim/mivon/blob/main/crates/mivon-compiler/src/frontend/compile_session.rs) (Compile Session), [`src/main.rs`](https://github.com/mivonsim/mivon/blob/main/src/main.rs) (CLI Runner), [`crates/mivon-gui/src/app.rs`](https://github.com/mivonsim/mivon/blob/main/crates/mivon-gui/src/app.rs) (GUI App)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_entry["User Interfaces"]
  node_cli["CLI Runner<br/>[main.rs]"]
  node_gui["GUI App<br/>[app.rs]"]
end

subgraph group_compile["Compile Pipeline"]
  node_preprocess["Preprocessor<br/>[preprocessor.rs]"]
  node_lexer["Lexer<br/>[lexer.rs]"]
  node_parser["Parser<br/>[lib.rs]"]
  node_ast["AST<br/>[lib.rs]"]
  node_elaborator["Elaborator<br/>[lib.rs]"]
  node_compiler["Compile Session<br/>[compile_session.rs]"]
  node_cache[("Incremental Cache<br/>[pipeline.rs]")]
  node_ir["Simulation IR<br/>[ir.rs]"]
end

subgraph group_simulation["Simulation"]
  node_engine["Simulation Engine<br/>[mod.rs]"]
  node_scheduler["Event Scheduler<br/>[mod.rs]"]
  node_uvm["UVM Runtime<br/>[mod.rs]"]
  node_cosim["Co-simulation Server<br/>[server.rs]"]
end

subgraph group_analysis["Verification Outputs"]
  node_coverage[("Coverage Database<br/>[coverage_db.rs]")]
  node_waveform["Waveform Writers<br/>[mod.rs]"]
end

subgraph group_extensions["Additional Capabilities"]
  node_synth["Synthesis<br/>[lib.rs]"]
  node_formal["Formal Verification<br/>[lib.rs]"]
  node_emulator["CPU Emulator<br/>[lib.rs]"]
  node_fuzz["Fuzz Testing<br/>[lib.rs]"]
end

node_user(("RTL User"))
node_source["SystemVerilog"]
node_external_sim(("External Simulator"))
node_wave_output["VCD / FST"]

node_user -->|"invokes"| node_cli
node_user -->|"uses"| node_gui
node_user -->|"provides"| node_source
node_cli -->|"loads"| node_source
node_cli -->|"starts compile"| node_compiler
node_gui -->|"compiles project"| node_compiler
node_compiler -->|"preprocesses"| node_preprocess
node_preprocess -->|"passes source"| node_lexer
node_lexer -->|"passes tokens"| node_parser
node_parser -->|"produces AST"| node_ast
node_ast -->|"elaborates"| node_elaborator
node_elaborator -->|"lowers"| node_ir
node_compiler -->|"populates"| node_cache
node_compiler -->|"starts simulation"| node_engine
node_ir -->|"design input"| node_engine
node_engine -->|"dispatches events"| node_scheduler
node_engine -->|"executes UVM"| node_uvm
node_engine -->|"records coverage"| node_coverage
node_engine -->|"records signals"| node_waveform
node_waveform -->|"writes"| node_wave_output
node_external_sim -.->|"connects"| node_cosim
node_cosim -.->|"exchanges signals"| node_engine
node_user -->|"requests synthesis"| node_synth
node_user -->|"requests verification"| node_formal
node_user -->|"runs emulation"| node_emulator
node_user -->|"runs fuzzing"| node_fuzz

click node_cli "https://github.com/mivonsim/mivon/blob/main/src/main.rs"
click node_gui "https://github.com/mivonsim/mivon/blob/main/crates/mivon-gui/src/app.rs"
click node_preprocess "https://github.com/mivonsim/mivon/blob/main/crates/mivon-parser/src/preprocessor.rs"
click node_lexer "https://github.com/mivonsim/mivon/blob/main/crates/mivon-parser/src/lexer.rs"
click node_parser "https://github.com/mivonsim/mivon/blob/main/crates/mivon-parser/src/lib.rs"
click node_ast "https://github.com/mivonsim/mivon/blob/main/crates/mivon-ast/src/lib.rs"
click node_elaborator "https://github.com/mivonsim/mivon/blob/main/crates/mivon-elaboration/src/lib.rs"
click node_compiler "https://github.com/mivonsim/mivon/blob/main/crates/mivon-compiler/src/frontend/compile_session.rs"
click node_cache "https://github.com/mivonsim/mivon/blob/main/crates/mivon-compiler/src/micd/cache/pipeline.rs"
click node_ir "https://github.com/mivonsim/mivon/blob/main/crates/mivon-ir/src/ir.rs"
click node_engine "https://github.com/mivonsim/mivon/blob/main/crates/mivon-simulator/src/simulator/engine/mod.rs"
click node_scheduler "https://github.com/mivonsim/mivon/blob/main/crates/mivon-simulator/src/simulator/engine/scheduler/mod.rs"
click node_uvm "https://github.com/mivonsim/mivon/blob/main/crates/mivon-simulator/src/simulator/engine/uvm/mod.rs"
click node_cosim "https://github.com/mivonsim/mivon/blob/main/crates/mivon-simulator/src/simulator/cosim/server.rs"
click node_coverage "https://github.com/mivonsim/mivon/blob/main/crates/mivon-simulator/src/simulator/coverage_db.rs"
click node_waveform "https://github.com/mivonsim/mivon/blob/main/crates/mivon-simulator/src/waveform/mod.rs"
click node_synth "https://github.com/mivonsim/mivon/blob/main/crates/mivon-synth/src/lib.rs"
click node_formal "https://github.com/mivonsim/mivon/blob/main/crates/mivon-formal/src/lib.rs"
click node_emulator "https://github.com/mivonsim/mivon/blob/main/crates/mivon-emu/src/lib.rs"
click node_fuzz "https://github.com/mivonsim/mivon/blob/main/crates/mivon-fuzz/src/lib.rs"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_cli,node_gui,node_user toneBlue
class node_preprocess,node_lexer,node_parser,node_ast,node_elaborator,node_compiler,node_cache,node_ir toneAmber
class node_engine,node_scheduler,node_uvm,node_cosim toneMint
class node_coverage,node_waveform toneRose
class node_synth,node_formal,node_emulator,node_fuzz,node_source,node_external_sim,node_wave_output toneIndigo
```

## Components

### User Interfaces

- [CLI Runner](https://github.com/mivonsim/mivon/blob/main/src/main.rs): `src/main.rs`
- [GUI App](https://github.com/mivonsim/mivon/blob/main/crates/mivon-gui/src/app.rs): `crates/mivon-gui/src/app.rs`

### Compile Pipeline

- [Preprocessor](https://github.com/mivonsim/mivon/blob/main/crates/mivon-parser/src/preprocessor.rs): `crates/mivon-parser/src/preprocessor.rs`
- [Lexer](https://github.com/mivonsim/mivon/blob/main/crates/mivon-parser/src/lexer.rs): `crates/mivon-parser/src/lexer.rs`
- [Parser](https://github.com/mivonsim/mivon/blob/main/crates/mivon-parser/src/lib.rs): `crates/mivon-parser/src/lib.rs`
- [AST](https://github.com/mivonsim/mivon/blob/main/crates/mivon-ast/src/lib.rs): `crates/mivon-ast/src/lib.rs`
- [Elaborator](https://github.com/mivonsim/mivon/blob/main/crates/mivon-elaboration/src/lib.rs): `crates/mivon-elaboration/src/lib.rs`
- [Compile Session](https://github.com/mivonsim/mivon/blob/main/crates/mivon-compiler/src/frontend/compile_session.rs): `crates/mivon-compiler/src/frontend/compile_session.rs`
- [Incremental Cache](https://github.com/mivonsim/mivon/blob/main/crates/mivon-compiler/src/micd/cache/pipeline.rs): `crates/mivon-compiler/src/micd/cache/pipeline.rs`
- [Simulation IR](https://github.com/mivonsim/mivon/blob/main/crates/mivon-ir/src/ir.rs): `crates/mivon-ir/src/ir.rs`

### Simulation

- [Simulation Engine](https://github.com/mivonsim/mivon/blob/main/crates/mivon-simulator/src/simulator/engine/mod.rs): `crates/mivon-simulator/src/simulator/engine/mod.rs`
- [Event Scheduler](https://github.com/mivonsim/mivon/blob/main/crates/mivon-simulator/src/simulator/engine/scheduler/mod.rs): `crates/mivon-simulator/src/simulator/engine/scheduler/mod.rs`
- [UVM Runtime](https://github.com/mivonsim/mivon/blob/main/crates/mivon-simulator/src/simulator/engine/uvm/mod.rs): `crates/mivon-simulator/src/simulator/engine/uvm/mod.rs`
- [Co-simulation Server](https://github.com/mivonsim/mivon/blob/main/crates/mivon-simulator/src/simulator/cosim/server.rs): `crates/mivon-simulator/src/simulator/cosim/server.rs`

### Verification Outputs

- [Coverage Database](https://github.com/mivonsim/mivon/blob/main/crates/mivon-simulator/src/simulator/coverage_db.rs): `crates/mivon-simulator/src/simulator/coverage_db.rs`
- [Waveform Writers](https://github.com/mivonsim/mivon/blob/main/crates/mivon-simulator/src/waveform/mod.rs): `crates/mivon-simulator/src/waveform/mod.rs`

### Additional Capabilities

- [Synthesis](https://github.com/mivonsim/mivon/blob/main/crates/mivon-synth/src/lib.rs): `crates/mivon-synth/src/lib.rs`
- [Formal Verification](https://github.com/mivonsim/mivon/blob/main/crates/mivon-formal/src/lib.rs): `crates/mivon-formal/src/lib.rs`
- [CPU Emulator](https://github.com/mivonsim/mivon/blob/main/crates/mivon-emu/src/lib.rs): `crates/mivon-emu/src/lib.rs`
- [Fuzz Testing](https://github.com/mivonsim/mivon/blob/main/crates/mivon-fuzz/src/lib.rs): `crates/mivon-fuzz/src/lib.rs`

### Other components

- **RTL User**
- **SystemVerilog**
- **External Simulator**
- **VCD / FST**

## Connections

- RTL User → CLI Runner: invokes
- RTL User → GUI App: uses
- RTL User → SystemVerilog: provides
- CLI Runner → SystemVerilog: loads
- CLI Runner → Compile Session: starts compile
- GUI App → Compile Session: compiles project
- Compile Session → Preprocessor: preprocesses
- Preprocessor → Lexer: passes source
- Lexer → Parser: passes tokens
- Parser → AST: produces AST
- AST → Elaborator: elaborates
- Elaborator → Simulation IR: lowers
- Compile Session → Incremental Cache: populates
- Compile Session → Simulation Engine: starts simulation
- Simulation IR → Simulation Engine: design input
- Simulation Engine → Event Scheduler: dispatches events
- Simulation Engine → UVM Runtime: executes UVM
- Simulation Engine → Coverage Database: records coverage
- Simulation Engine → Waveform Writers: records signals
- Waveform Writers → VCD / FST: writes
- External Simulator → Co-simulation Server: connects
- Co-simulation Server → Simulation Engine: exchanges signals
- RTL User → Synthesis: requests synthesis
- RTL User → Formal Verification: requests verification
- RTL User → CPU Emulator: runs emulation
- RTL User → Fuzz Testing: runs fuzzing