How mihir8181/vlsi-design-digital-system works
This repository is a collection of Cadence Virtuoso digital VLSI designs, from logic gates through arithmetic, selection, and sequential circuits. The documented workflow is circuit schematic and symbol design, testbench simulation, physical layout, and extracted-layout/post-layout checks including DRC and LVS. The README supports these stages and the gate-to-circuit relationship, but no source excerpts were supplied, so detailed inter-circuit wiring and simulation-to-layout automation are not inferred.
Main entry points: Logic Gates Logic Gates · 1Bit_HalfADDER.7z Half Adder · 1Bit_FullADDER.7z Full Adder · 1Bit_Adder_Subtract 1-Bit Add/Subtract
Components 19
Logic Foundations
- Logic Gates
Logic Gates - Inverter and TG
Logic Gates
Arithmetic Circuits
- Half Adder
1Bit_HalfADDER.7z - Full Adder
1Bit_FullADDER.7z - 1-Bit Add/Subtract
1Bit_Adder_Subtract - 4-Bit Adder
4Bit_Adder/4Bit_Adder - 4-Bit Multiplier
4bit_Multipler/4Bit_Multiplier - 4-Bit Divider
4bit _Divider/4Bit_Divider - ALU
ALU/ALU
Selection and State
- 2:1 MUX
8_1MUX - 8:1 MUX
8_1MUX/8#3a1MUX - D Flip-Flop
D_FlipFlop/D_FlipFlop_2
Design Validation
- Schematics and Symbols
- Testbenches
- Simulation Results
- Physical Layouts
- Extracted Layouts
- DRC and LVS
Other components
- Circuit Designer
Connections 17
- Circuit Designer → Schematics and Symbols: designs
- Logic Gates → Inverter and TG: used to design
- Logic Gates → Half Adder: used to design
- Logic Gates → Full Adder: used to design
- Logic Gates → 1-Bit Add/Subtract: used to design
- Logic Gates → 4-Bit Adder: used to design
- Logic Gates → 4-Bit Multiplier: used to design
- Logic Gates → 4-Bit Divider: used to design
- Logic Gates → ALU: used to design
- Logic Gates → 2:1 MUX: used to design
- Logic Gates → 8:1 MUX: used to design
- Logic Gates → D Flip-Flop: used to design
- Schematics and Symbols → Testbenches: exercise designs
- Testbenches → Simulation Results: produce results
- Schematics and Symbols → Physical Layouts: implemented as
- Physical Layouts → Extracted Layouts: extracted for
- Extracted Layouts → DRC and LVS: checked by