# mihir8181/vlsi-design-digital-system architecture

> Architecture diagram of the GitHub repository mihir8181/vlsi-design-digital-system, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-26). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/mihir8181/vlsi-design-digital-system
- Repository: https://github.com/mihir8181/vlsi-design-digital-system

## Overview

This repository is a collection of Cadence Virtuoso digital VLSI designs, from logic gates through arithmetic, selection, and sequential circuits. The documented workflow is circuit schematic and symbol design, testbench simulation, physical layout, and extracted-layout/post-layout checks including DRC and LVS. The README supports these stages and the gate-to-circuit relationship, but no source excerpts were supplied, so detailed inter-circuit wiring and simulation-to-layout automation are not inferred.

Main entry points: [`Logic Gates`](https://github.com/mihir8181/vlsi-design-digital-system/tree/master/Logic%20Gates) (Logic Gates), [`1Bit_HalfADDER.7z`](https://github.com/mihir8181/vlsi-design-digital-system/blob/master/1Bit_HalfADDER.7z) (Half Adder), [`1Bit_FullADDER.7z`](https://github.com/mihir8181/vlsi-design-digital-system/blob/master/1Bit_FullADDER.7z) (Full Adder), [`1Bit_Adder_Subtract`](https://github.com/mihir8181/vlsi-design-digital-system/tree/master/1Bit_Adder_Subtract) (1-Bit Add/Subtract)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_logic["Logic Foundations"]
  node_gates["Logic Gates"]
  node_inverter_tg["Inverter and TG"]
end

subgraph group_arithmetic["Arithmetic Circuits"]
  node_half_adder["Half Adder<br/>[1Bit_HalfADDER.7z]"]
  node_full_adder["Full Adder<br/>[1Bit_FullADDER.7z]"]
  node_addsub["1-Bit Add/Subtract"]
  node_adder4["4-Bit Adder"]
  node_multiplier4["4-Bit Multiplier"]
  node_divider4["4-Bit Divider"]
  node_alu["ALU"]
end

subgraph group_other["Selection and State"]
  node_mux2["2:1 MUX"]
  node_mux8["8:1 MUX"]
  node_dff["D Flip-Flop"]
end

subgraph group_implementation["Design Validation"]
  node_schematics["Schematics and Symbols"]
  node_testbenches["Testbenches"]
  node_simulation["Simulation Results"]
  node_layouts["Physical Layouts"]
  node_extracted["Extracted Layouts"]
  node_checks["DRC and LVS"]
end

node_designer(("Circuit Designer"))

node_designer -->|"designs"| node_schematics
node_gates -->|"used to design"| node_inverter_tg
node_gates -->|"used to design"| node_half_adder
node_gates -->|"used to design"| node_full_adder
node_gates -->|"used to design"| node_addsub
node_gates -->|"used to design"| node_adder4
node_gates -->|"used to design"| node_multiplier4
node_gates -->|"used to design"| node_divider4
node_gates -->|"used to design"| node_alu
node_gates -->|"used to design"| node_mux2
node_gates -->|"used to design"| node_mux8
node_gates -->|"used to design"| node_dff
node_schematics -->|"exercise designs"| node_testbenches
node_testbenches -->|"produce results"| node_simulation
node_schematics -->|"implemented as"| node_layouts
node_layouts -->|"extracted for"| node_extracted
node_extracted -->|"checked by"| node_checks

click node_gates "https://github.com/mihir8181/vlsi-design-digital-system/tree/master/Logic%20Gates"
click node_inverter_tg "https://github.com/mihir8181/vlsi-design-digital-system/tree/master/Logic%20Gates"
click node_half_adder "https://github.com/mihir8181/vlsi-design-digital-system/blob/master/1Bit_HalfADDER.7z"
click node_full_adder "https://github.com/mihir8181/vlsi-design-digital-system/blob/master/1Bit_FullADDER.7z"
click node_addsub "https://github.com/mihir8181/vlsi-design-digital-system/tree/master/1Bit_Adder_Subtract"
click node_adder4 "https://github.com/mihir8181/vlsi-design-digital-system/tree/master/4Bit_Adder/4Bit_Adder"
click node_multiplier4 "https://github.com/mihir8181/vlsi-design-digital-system/tree/master/4bit_Multipler/4Bit_Multiplier"
click node_divider4 "https://github.com/mihir8181/vlsi-design-digital-system/tree/master/4bit%20_Divider/4Bit_Divider"
click node_alu "https://github.com/mihir8181/vlsi-design-digital-system/tree/master/ALU/ALU"
click node_mux2 "https://github.com/mihir8181/vlsi-design-digital-system/tree/master/8_1MUX"
click node_mux8 "https://github.com/mihir8181/vlsi-design-digital-system/tree/master/8_1MUX/8%233a1MUX"
click node_dff "https://github.com/mihir8181/vlsi-design-digital-system/tree/master/D_FlipFlop/D_FlipFlop_2"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_gates,node_inverter_tg toneBlue
class node_half_adder,node_full_adder,node_addsub,node_adder4,node_multiplier4,node_divider4,node_alu toneAmber
class node_mux2,node_mux8,node_dff toneMint
class node_schematics,node_testbenches,node_simulation,node_layouts,node_extracted,node_checks toneRose
class node_designer toneIndigo
```

## Components

### Logic Foundations

- [Logic Gates](https://github.com/mihir8181/vlsi-design-digital-system/tree/master/Logic%20Gates): `Logic Gates`
- [Inverter and TG](https://github.com/mihir8181/vlsi-design-digital-system/tree/master/Logic%20Gates): `Logic Gates`

### Arithmetic Circuits

- [Half Adder](https://github.com/mihir8181/vlsi-design-digital-system/blob/master/1Bit_HalfADDER.7z): `1Bit_HalfADDER.7z`
- [Full Adder](https://github.com/mihir8181/vlsi-design-digital-system/blob/master/1Bit_FullADDER.7z): `1Bit_FullADDER.7z`
- [1-Bit Add/Subtract](https://github.com/mihir8181/vlsi-design-digital-system/tree/master/1Bit_Adder_Subtract): `1Bit_Adder_Subtract`
- [4-Bit Adder](https://github.com/mihir8181/vlsi-design-digital-system/tree/master/4Bit_Adder/4Bit_Adder): `4Bit_Adder/4Bit_Adder`
- [4-Bit Multiplier](https://github.com/mihir8181/vlsi-design-digital-system/tree/master/4bit_Multipler/4Bit_Multiplier): `4bit_Multipler/4Bit_Multiplier`
- [4-Bit Divider](https://github.com/mihir8181/vlsi-design-digital-system/tree/master/4bit%20_Divider/4Bit_Divider): `4bit _Divider/4Bit_Divider`
- [ALU](https://github.com/mihir8181/vlsi-design-digital-system/tree/master/ALU/ALU): `ALU/ALU`

### Selection and State

- [2:1 MUX](https://github.com/mihir8181/vlsi-design-digital-system/tree/master/8_1MUX): `8_1MUX`
- [8:1 MUX](https://github.com/mihir8181/vlsi-design-digital-system/tree/master/8_1MUX/8%233a1MUX): `8_1MUX/8#3a1MUX`
- [D Flip-Flop](https://github.com/mihir8181/vlsi-design-digital-system/tree/master/D_FlipFlop/D_FlipFlop_2): `D_FlipFlop/D_FlipFlop_2`

### Design Validation

- **Schematics and Symbols**
- **Testbenches**
- **Simulation Results**
- **Physical Layouts**
- **Extracted Layouts**
- **DRC and LVS**

### Other components

- **Circuit Designer**

## Connections

- Circuit Designer → Schematics and Symbols: designs
- Logic Gates → Inverter and TG: used to design
- Logic Gates → Half Adder: used to design
- Logic Gates → Full Adder: used to design
- Logic Gates → 1-Bit Add/Subtract: used to design
- Logic Gates → 4-Bit Adder: used to design
- Logic Gates → 4-Bit Multiplier: used to design
- Logic Gates → 4-Bit Divider: used to design
- Logic Gates → ALU: used to design
- Logic Gates → 2:1 MUX: used to design
- Logic Gates → 8:1 MUX: used to design
- Logic Gates → D Flip-Flop: used to design
- Schematics and Symbols → Testbenches: exercise designs
- Testbenches → Simulation Results: produce results
- Schematics and Symbols → Physical Layouts: implemented as
- Physical Layouts → Extracted Layouts: extracted for
- Extracted Layouts → DRC and LVS: checked by