How mh-electronic/risc-v-processor-design works
This is an RV32I processor project progressing from a single-cycle core through a classic five-stage pipeline to an adaptive pipeline, with bare-metal software and memory-mapped peripherals. Firmware runs on the adaptive core, selects pipeline mode through a CSR, and writes GPIO for the LED example. The README documents forwarding, hazard mitigation, and pipeline-stage unification; detailed wiring for those features is not shown in the sampled source, so only documented high-level relationships are drawn.
Main entry points: rtl/riscv_top.v Adaptive core · rtl/riscv_top.v Five-stage core · bus_decoder.v Peripheral decoder · main.c LED firmware
Components 17
Single Cycle
- Single-cycle core
Phase1_Single_Cycle/rtl/riscv_top.v - Instruction control
Phase1_Single_Cycle/rtl/control_unit.v - ALU and decode
Phase1_Single_Cycle/rtl/alu.v
Five Stage
- Five-stage core
Phase2_5_Stage/rtl/riscv_top.v - Hazard handling
Phase2_5_Stage/rtl/hazard_detection_unit.v - Operand forwarding
Phase2_5_Stage/rtl/forwarding_unit.v - Pipeline registers
Phase2_5_Stage/rtl/reg_if_id.v
Adaptive Core
- Adaptive core
Phase3_Adaptive/rtl/riscv_top.v - Peripheral decoder
Phase3_Adaptive/rtl/bus_decoder.v - Instruction memory
Phase3_Adaptive/rtl/instr_rom_dual_port.v - Data memory
Phase3_Adaptive/rtl/data_ram.v - Mode CSR
Phase3_Adaptive/rtl/csr_unit.v
Software And I/O
- LED firmware
Phase3_Adaptive/software/main.c - GPIO peripheral
Phase3_Adaptive/rtl/gpio_module.v - Timer peripheral
Phase3_Adaptive/rtl/timer_module.v - UART bridge
Phase3_Adaptive/rtl/uart_bridge.v
Other components
- Firmware workload
Connections 18
- Firmware workload → Single-cycle core: runs instructions
- Firmware workload → Five-stage core: runs instructions
- Firmware workload → LED firmware: provides workload
- LED firmware → Adaptive core: executes on
- Single-cycle core → Instruction control: uses control
- Single-cycle core → ALU and decode: executes operations
- Five-stage core → Hazard handling: checks hazards
- Five-stage core → Operand forwarding: forwards operands
- Five-stage core → Pipeline registers: passes stage state
- Adaptive core → Peripheral decoder: dispatches peripheral accesses
- Adaptive core → Instruction memory: fetches instructions
- Adaptive core → Data memory: accesses data
- Adaptive core → Mode CSR: reads and writes mode
- LED firmware → Mode CSR: selects pipeline mode
- LED firmware → GPIO peripheral: writes LED data
- Peripheral decoder → GPIO peripheral: decodes GPIO access
- Peripheral decoder → Timer peripheral: decodes timer access
- Peripheral decoder → UART bridge: decodes UART access