# mh-electronic/risc-v-processor-design architecture

> Architecture diagram of the GitHub repository mh-electronic/risc-v-processor-design, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-28). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/mh-electronic/risc-v-processor-design
- Repository: https://github.com/mh-electronic/risc-v-processor-design

## Overview

This is an RV32I processor project progressing from a single-cycle core through a classic five-stage pipeline to an adaptive pipeline, with bare-metal software and memory-mapped peripherals. Firmware runs on the adaptive core, selects pipeline mode through a CSR, and writes GPIO for the LED example. The README documents forwarding, hazard mitigation, and pipeline-stage unification; detailed wiring for those features is not shown in the sampled source, so only documented high-level relationships are drawn.

Main entry points: [`Phase3_Adaptive/rtl/riscv_top.v`](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/rtl/riscv_top.v) (Adaptive core), [`Phase2_5_Stage/rtl/riscv_top.v`](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase2_5_Stage/rtl/riscv_top.v) (Five-stage core), [`Phase3_Adaptive/rtl/bus_decoder.v`](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/rtl/bus_decoder.v) (Peripheral decoder), [`Phase3_Adaptive/software/main.c`](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/software/main.c) (LED firmware)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_baseline["Single Cycle"]
  node_core1["Single-cycle core<br/>[riscv_top.v]"]
  node_control1["Instruction control<br/>[control_unit.v]"]
  node_execute1["ALU and decode<br/>[alu.v]"]
end

subgraph group_pipeline["Five Stage"]
  node_core2["Five-stage core<br/>[riscv_top.v]"]
  node_hazard2["Hazard handling"]
  node_forward2["Operand forwarding<br/>[forwarding_unit.v]"]
  node_stages2["Pipeline registers<br/>[reg_if_id.v]"]
end

subgraph group_adaptive["Adaptive Core"]
  node_core3["Adaptive core<br/>[riscv_top.v]"]
  node_bus["Peripheral decoder<br/>[bus_decoder.v]"]
  node_rom[("Instruction memory")]
  node_ram[("Data memory<br/>[data_ram.v]")]
  node_csr["Mode CSR<br/>[csr_unit.v]"]
end

subgraph group_software_io["Software And I/O"]
  node_firmware["LED firmware<br/>[main.c]"]
  node_gpio["GPIO peripheral<br/>[gpio_module.v]"]
  node_timer["Timer peripheral<br/>[timer_module.v]"]
  node_uart["UART bridge<br/>[uart_bridge.v]"]
end

node_user(("Firmware workload"))

node_user -->|"runs instructions"| node_core1
node_user -->|"runs instructions"| node_core2
node_user -->|"provides workload"| node_firmware
node_firmware -->|"executes on"| node_core3
node_core1 -->|"uses control"| node_control1
node_core1 -->|"executes operations"| node_execute1
node_core2 -->|"checks hazards"| node_hazard2
node_core2 -->|"forwards operands"| node_forward2
node_core2 -->|"passes stage state"| node_stages2
node_core3 -->|"dispatches peripheral accesses"| node_bus
node_core3 -->|"fetches instructions"| node_rom
node_core3 -->|"accesses data"| node_ram
node_core3 -->|"reads and writes mode"| node_csr
node_firmware -->|"selects pipeline mode"| node_csr
node_firmware -->|"writes LED data"| node_gpio
node_bus -->|"decodes GPIO access"| node_gpio
node_bus -->|"decodes timer access"| node_timer
node_bus -->|"decodes UART access"| node_uart

click node_core1 "https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase1_Single_Cycle/rtl/riscv_top.v"
click node_control1 "https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase1_Single_Cycle/rtl/control_unit.v"
click node_execute1 "https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase1_Single_Cycle/rtl/alu.v"
click node_core2 "https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase2_5_Stage/rtl/riscv_top.v"
click node_hazard2 "https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase2_5_Stage/rtl/hazard_detection_unit.v"
click node_forward2 "https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase2_5_Stage/rtl/forwarding_unit.v"
click node_stages2 "https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase2_5_Stage/rtl/reg_if_id.v"
click node_core3 "https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/rtl/riscv_top.v"
click node_bus "https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/rtl/bus_decoder.v"
click node_rom "https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/rtl/instr_rom_dual_port.v"
click node_ram "https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/rtl/data_ram.v"
click node_csr "https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/rtl/csr_unit.v"
click node_firmware "https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/software/main.c"
click node_gpio "https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/rtl/gpio_module.v"
click node_timer "https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/rtl/timer_module.v"
click node_uart "https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/rtl/uart_bridge.v"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_core1,node_control1,node_execute1 toneBlue
class node_core2,node_hazard2,node_forward2,node_stages2 toneAmber
class node_core3,node_bus,node_rom,node_ram,node_csr toneMint
class node_firmware,node_gpio,node_timer,node_uart toneRose
class node_user toneIndigo
```

## Components

### Single Cycle

- [Single-cycle core](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase1_Single_Cycle/rtl/riscv_top.v): `Phase1_Single_Cycle/rtl/riscv_top.v`
- [Instruction control](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase1_Single_Cycle/rtl/control_unit.v): `Phase1_Single_Cycle/rtl/control_unit.v`
- [ALU and decode](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase1_Single_Cycle/rtl/alu.v): `Phase1_Single_Cycle/rtl/alu.v`

### Five Stage

- [Five-stage core](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase2_5_Stage/rtl/riscv_top.v): `Phase2_5_Stage/rtl/riscv_top.v`
- [Hazard handling](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase2_5_Stage/rtl/hazard_detection_unit.v): `Phase2_5_Stage/rtl/hazard_detection_unit.v`
- [Operand forwarding](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase2_5_Stage/rtl/forwarding_unit.v): `Phase2_5_Stage/rtl/forwarding_unit.v`
- [Pipeline registers](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase2_5_Stage/rtl/reg_if_id.v): `Phase2_5_Stage/rtl/reg_if_id.v`

### Adaptive Core

- [Adaptive core](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/rtl/riscv_top.v): `Phase3_Adaptive/rtl/riscv_top.v`
- [Peripheral decoder](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/rtl/bus_decoder.v): `Phase3_Adaptive/rtl/bus_decoder.v`
- [Instruction memory](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/rtl/instr_rom_dual_port.v): `Phase3_Adaptive/rtl/instr_rom_dual_port.v`
- [Data memory](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/rtl/data_ram.v): `Phase3_Adaptive/rtl/data_ram.v`
- [Mode CSR](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/rtl/csr_unit.v): `Phase3_Adaptive/rtl/csr_unit.v`

### Software And I/O

- [LED firmware](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/software/main.c): `Phase3_Adaptive/software/main.c`
- [GPIO peripheral](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/rtl/gpio_module.v): `Phase3_Adaptive/rtl/gpio_module.v`
- [Timer peripheral](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/rtl/timer_module.v): `Phase3_Adaptive/rtl/timer_module.v`
- [UART bridge](https://github.com/mh-electronic/risc-v-processor-design/blob/main/Phase3_Adaptive/rtl/uart_bridge.v): `Phase3_Adaptive/rtl/uart_bridge.v`

### Other components

- **Firmware workload**

## Connections

- Firmware workload → Single-cycle core: runs instructions
- Firmware workload → Five-stage core: runs instructions
- Firmware workload → LED firmware: provides workload
- LED firmware → Adaptive core: executes on
- Single-cycle core → Instruction control: uses control
- Single-cycle core → ALU and decode: executes operations
- Five-stage core → Hazard handling: checks hazards
- Five-stage core → Operand forwarding: forwards operands
- Five-stage core → Pipeline registers: passes stage state
- Adaptive core → Peripheral decoder: dispatches peripheral accesses
- Adaptive core → Instruction memory: fetches instructions
- Adaptive core → Data memory: accesses data
- Adaptive core → Mode CSR: reads and writes mode
- LED firmware → Mode CSR: selects pipeline mode
- LED firmware → GPIO peripheral: writes LED data
- Peripheral decoder → GPIO peripheral: decodes GPIO access
- Peripheral decoder → Timer peripheral: decodes timer access
- Peripheral decoder → UART bridge: decodes UART access