How mgtm98/pcie5_phy works
This repository is a PCIe 5.0 PHY graduation project with a SystemVerilog verification environment and RTL design. The documented user workflow is to run the environment from tb/sim; the tree shows test, sequence, agent, and environment areas alongside RTL for link control, transmit/receive, and data handling. No source excerpts were provided, and the README does not describe internal calls or data flow, so the graph avoids asserting connections between those subsystems.
Main entry points: env UVM environment
Components 16
Verification environment
- PCIe test
tb/test - Test sequences
tb/sequences - Protocol agents
tb/agents - UVM environment
tb/env - Simulation tops
tb/top
PCIe link control
- Link state machines
rtl - Generation control
rtl/Gen_ctrl.v - Lane management
rtl/Lane_Management_Control.v
PHY datapath
- PIPE interface
rtl/PIPE_Data.v - Receive datapath
rtl/PIPE_Rx_Data.v - Transmit datapath
rtl/Master_Tx.v - Scrambling
rtl/Scrambler.v - Descrambling
rtl/Descrambler.v - FIFO buffering
rtl/FIFOV2.v - Lane unstriping
rtl/UnStriping.v
Other components
- Verification user
Connections 1
- Verification user → UVM environment: runs environment
README.md