# mgtm98/pcie5_phy architecture

> Architecture diagram of the GitHub repository mgtm98/pcie5_phy, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-11-10). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/mgtm98/pcie5_phy
- Repository: https://github.com/mgtm98/pcie5_phy

## Overview

This repository is a PCIe 5.0 PHY graduation project with a SystemVerilog verification environment and RTL design. The documented user workflow is to run the environment from `tb/sim`; the tree shows test, sequence, agent, and environment areas alongside RTL for link control, transmit/receive, and data handling. No source excerpts were provided, and the README does not describe internal calls or data flow, so the graph avoids asserting connections between those subsystems.

Main entry points: [`tb/env`](https://github.com/mgtm98/pcie5_phy/tree/master/tb/env) (UVM environment)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_verification["Verification environment"]
  node_test["PCIe test"]
  node_sequences["Test sequences"]
  node_agents["Protocol agents"]
  node_env["UVM environment"]
  node_tops["Simulation tops"]
end

subgraph group_protocol["PCIe link control"]
  node_link["Link state machines"]
  node_genctrl["Generation control<br/>[Gen_ctrl.v]"]
  node_lane["Lane management"]
end

subgraph group_datapath["PHY datapath"]
  node_pipe["PIPE interface<br/>[PIPE_Data.v]"]
  node_rx["Receive datapath<br/>[PIPE_Rx_Data.v]"]
  node_tx["Transmit datapath<br/>[Master_Tx.v]"]
  node_scramble["Scrambling<br/>[Scrambler.v]"]
  node_descramble["Descrambling<br/>[Descrambler.v]"]
  node_fifo["FIFO buffering<br/>[FIFOV2.v]"]
  node_unstripe["Lane unstriping<br/>[UnStriping.v]"]
end

node_user(("Verification user"))

node_user -->|"runs environment"| node_env

click node_test "https://github.com/mgtm98/pcie5_phy/tree/master/tb/test"
click node_sequences "https://github.com/mgtm98/pcie5_phy/tree/master/tb/sequences"
click node_agents "https://github.com/mgtm98/pcie5_phy/tree/master/tb/agents"
click node_env "https://github.com/mgtm98/pcie5_phy/tree/master/tb/env"
click node_tops "https://github.com/mgtm98/pcie5_phy/tree/master/tb/top"
click node_link "https://github.com/mgtm98/pcie5_phy/tree/master/rtl"
click node_genctrl "https://github.com/mgtm98/pcie5_phy/blob/master/rtl/Gen_ctrl.v"
click node_lane "https://github.com/mgtm98/pcie5_phy/blob/master/rtl/Lane_Management_Control.v"
click node_pipe "https://github.com/mgtm98/pcie5_phy/blob/master/rtl/PIPE_Data.v"
click node_rx "https://github.com/mgtm98/pcie5_phy/blob/master/rtl/PIPE_Rx_Data.v"
click node_tx "https://github.com/mgtm98/pcie5_phy/blob/master/rtl/Master_Tx.v"
click node_scramble "https://github.com/mgtm98/pcie5_phy/blob/master/rtl/Scrambler.v"
click node_descramble "https://github.com/mgtm98/pcie5_phy/blob/master/rtl/Descrambler.v"
click node_fifo "https://github.com/mgtm98/pcie5_phy/blob/master/rtl/FIFOV2.v"
click node_unstripe "https://github.com/mgtm98/pcie5_phy/blob/master/rtl/UnStriping.v"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_test,node_sequences,node_agents,node_env,node_tops,node_user toneBlue
class node_link,node_genctrl,node_lane toneAmber
class node_pipe,node_rx,node_tx,node_scramble,node_descramble,node_fifo,node_unstripe toneMint
```

## Components

### Verification environment

- [PCIe test](https://github.com/mgtm98/pcie5_phy/tree/master/tb/test): `tb/test`
- [Test sequences](https://github.com/mgtm98/pcie5_phy/tree/master/tb/sequences): `tb/sequences`
- [Protocol agents](https://github.com/mgtm98/pcie5_phy/tree/master/tb/agents): `tb/agents`
- [UVM environment](https://github.com/mgtm98/pcie5_phy/tree/master/tb/env): `tb/env`
- [Simulation tops](https://github.com/mgtm98/pcie5_phy/tree/master/tb/top): `tb/top`

### PCIe link control

- [Link state machines](https://github.com/mgtm98/pcie5_phy/tree/master/rtl): `rtl`
- [Generation control](https://github.com/mgtm98/pcie5_phy/blob/master/rtl/Gen_ctrl.v): `rtl/Gen_ctrl.v`
- [Lane management](https://github.com/mgtm98/pcie5_phy/blob/master/rtl/Lane_Management_Control.v): `rtl/Lane_Management_Control.v`

### PHY datapath

- [PIPE interface](https://github.com/mgtm98/pcie5_phy/blob/master/rtl/PIPE_Data.v): `rtl/PIPE_Data.v`
- [Receive datapath](https://github.com/mgtm98/pcie5_phy/blob/master/rtl/PIPE_Rx_Data.v): `rtl/PIPE_Rx_Data.v`
- [Transmit datapath](https://github.com/mgtm98/pcie5_phy/blob/master/rtl/Master_Tx.v): `rtl/Master_Tx.v`
- [Scrambling](https://github.com/mgtm98/pcie5_phy/blob/master/rtl/Scrambler.v): `rtl/Scrambler.v`
- [Descrambling](https://github.com/mgtm98/pcie5_phy/blob/master/rtl/Descrambler.v): `rtl/Descrambler.v`
- [FIFO buffering](https://github.com/mgtm98/pcie5_phy/blob/master/rtl/FIFOV2.v): `rtl/FIFOV2.v`
- [Lane unstriping](https://github.com/mgtm98/pcie5_phy/blob/master/rtl/UnStriping.v): `rtl/UnStriping.v`

### Other components

- **Verification user**

## Connections

- Verification user → UVM environment: runs environment (evidence: `README.md`)