# kasirga-kizil/tekno-kizil architecture

> Architecture diagram of the GitHub repository kasirga-kizil/tekno-kizil, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-28). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/kasirga-kizil/tekno-kizil
- Repository: https://github.com/kasirga-kizil/tekno-kizil

## Overview

This repository documents the KIZIL RISC-V processor project, but the supplied tree does not include the processor RTL itself. The visible runtime-oriented material centers on bare-metal examples, processor validation and benchmark programs, plus host-side programming and simulation utilities. A typical visible workflow is to prepare firmware for a demo, load it onto a board, and observe UART output; separate validation programs exercise ISA, debug and benchmark behavior. README-described processor structure is retained as context, but its internal wiring cannot be traced from the available files. Arrows reflect only the sampled source and explicit documentation.

Main entry points: [`testler/uart-demo/main.c`](https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/uart-demo/main.c) (UART example), [`testler/baremetal-tekno-sw-edit/software/tekno_example/tekno_example.c`](https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/baremetal-tekno-sw-edit/software/tekno_example/tekno_example.c) (Bare-metal example), [`araclar/teknofest_ram_seri_port.py`](https://github.com/kasirga-kizil/tekno-kizil/blob/main/araclar/teknofest_ram_seri_port.py) (Serial programmer), [`araclar/uart_programlayici/uart_send_data.py`](https://github.com/kasirga-kizil/tekno-kizil/blob/main/araclar/uart_programlayici/uart_send_data.py) (UART sender)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_processor["KIZIL processor"]
  node_kizil["KIZIL CPU"]
  node_pipeline["Pipeline core"]
  node_system["System design"]
end

subgraph group_firmware["Firmware examples"]
  node_uart_demo["UART example<br/>[main.c]"]
  node_baremetal_example["Bare-metal example<br/>[tekno_example.c]"]
  node_drivers["Peripheral drivers<br/>[uart_driver.c]"]
end

subgraph group_validation["Processor validation"]
  node_coremark["CoreMark benchmark<br/>[core_main.c]"]
  node_dhrystone["Dhrystone benchmark<br/>[dhry_1.c]"]
  node_riscv_arch["Architecture tests<br/>[encoding.h]"]
  node_riscv_tests["ISA tests<br/>[get_static_hex.py]"]
  node_debug_tests["Debug tests<br/>[gdbserver.py]"]
  node_sim_tests["Simulation tests<br/>[riscv_tests.py]"]
end

subgraph group_tools["Host tools"]
  node_log_parser["Trace parser<br/>[log_parser.py]"]
  node_serial_programmer["Serial programmer"]
  node_uart_sender["UART sender<br/>[uart_send_data.py]"]
  node_openlane_helper["OpenLane helper<br/>[auto_openlane.py]"]
end

node_developer(("Developer"))
node_board["Target board"]
node_spike["Spike simulator"]

node_developer -->|"runs firmware"| node_uart_demo
node_uart_demo -->|"uses UART"| node_drivers
node_uart_demo -->|"communicates by UART"| node_board
node_developer -->|"programs target"| node_serial_programmer
node_serial_programmer -->|"sends firmware"| node_board
node_developer -->|"sends data"| node_uart_sender
node_uart_sender -->|"writes serial"| node_board
node_developer -->|"runs firmware"| node_baremetal_example
node_baremetal_example -->|"uses drivers"| node_drivers
node_developer -->|"runs benchmark"| node_coremark
node_developer -->|"runs benchmark"| node_dhrystone
node_developer -->|"runs tests"| node_riscv_arch
node_developer -->|"runs tests"| node_riscv_tests
node_developer -->|"runs debug tests"| node_debug_tests
node_developer -->|"runs simulations"| node_sim_tests
node_developer -->|"parses trace"| node_log_parser
node_spike -.->|"produces log"| node_log_parser
node_developer -->|"invokes helper"| node_openlane_helper
node_kizil -->|"includes"| node_pipeline
node_kizil -->|"described by"| node_system

click node_uart_demo "https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/uart-demo/main.c"
click node_baremetal_example "https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/baremetal-tekno-sw-edit/software/tekno_example/tekno_example.c"
click node_drivers "https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/baremetal-tekno-sw-edit/drivers/src/uart_driver.c"
click node_coremark "https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/coremark/core_main.c"
click node_dhrystone "https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/dhrystone/dhry_1.c"
click node_riscv_arch "https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/riscv-arch-test/riscv-test-env/encoding.h"
click node_riscv_tests "https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/riscv-tests/isa/get_static_hex.py"
click node_debug_tests "https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/riscv-tests/debug/gdbserver.py"
click node_sim_tests "https://github.com/kasirga-kizil/tekno-kizil/blob/main/verilog-simulasyonu/testler/riscv_tests.py"
click node_log_parser "https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/aapg/log_parser.py"
click node_serial_programmer "https://github.com/kasirga-kizil/tekno-kizil/blob/main/araclar/teknofest_ram_seri_port.py"
click node_uart_sender "https://github.com/kasirga-kizil/tekno-kizil/blob/main/araclar/uart_programlayici/uart_send_data.py"
click node_openlane_helper "https://github.com/kasirga-kizil/tekno-kizil/blob/main/araclar/auto_openlane.py"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_kizil,node_pipeline,node_system toneBlue
class node_uart_demo,node_baremetal_example,node_drivers toneAmber
class node_coremark,node_dhrystone,node_riscv_arch,node_riscv_tests,node_debug_tests,node_sim_tests toneMint
class node_log_parser,node_serial_programmer,node_uart_sender,node_openlane_helper toneRose
class node_developer,node_board,node_spike toneIndigo
```

## Components

### KIZIL processor

- **KIZIL CPU**
- **Pipeline core**
- **System design**

### Firmware examples

- [UART example](https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/uart-demo/main.c): `testler/uart-demo/main.c`
- [Bare-metal example](https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/baremetal-tekno-sw-edit/software/tekno_example/tekno_example.c): `testler/baremetal-tekno-sw-edit/software/tekno_example/tekno_example.c`
- [Peripheral drivers](https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/baremetal-tekno-sw-edit/drivers/src/uart_driver.c): `testler/baremetal-tekno-sw-edit/drivers/src/uart_driver.c`

### Processor validation

- [CoreMark benchmark](https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/coremark/core_main.c): `testler/coremark/core_main.c`
- [Dhrystone benchmark](https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/dhrystone/dhry_1.c): `testler/dhrystone/dhry_1.c`
- [Architecture tests](https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/riscv-arch-test/riscv-test-env/encoding.h): `testler/riscv-arch-test/riscv-test-env/encoding.h`
- [ISA tests](https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/riscv-tests/isa/get_static_hex.py): `testler/riscv-tests/isa/get_static_hex.py`
- [Debug tests](https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/riscv-tests/debug/gdbserver.py): `testler/riscv-tests/debug/gdbserver.py`
- [Simulation tests](https://github.com/kasirga-kizil/tekno-kizil/blob/main/verilog-simulasyonu/testler/riscv_tests.py): `verilog-simulasyonu/testler/riscv_tests.py`

### Host tools

- [Trace parser](https://github.com/kasirga-kizil/tekno-kizil/blob/main/testler/aapg/log_parser.py): `testler/aapg/log_parser.py`
- [Serial programmer](https://github.com/kasirga-kizil/tekno-kizil/blob/main/araclar/teknofest_ram_seri_port.py): `araclar/teknofest_ram_seri_port.py`
- [UART sender](https://github.com/kasirga-kizil/tekno-kizil/blob/main/araclar/uart_programlayici/uart_send_data.py): `araclar/uart_programlayici/uart_send_data.py`
- [OpenLane helper](https://github.com/kasirga-kizil/tekno-kizil/blob/main/araclar/auto_openlane.py): `araclar/auto_openlane.py`

### Other components

- **Developer**
- **Target board**
- **Spike simulator**

## Connections

- Developer → UART example: runs firmware
- UART example → Peripheral drivers: uses UART
- UART example → Target board: communicates by UART
- Developer → Serial programmer: programs target
- Serial programmer → Target board: sends firmware
- Developer → UART sender: sends data
- UART sender → Target board: writes serial
- Developer → Bare-metal example: runs firmware
- Bare-metal example → Peripheral drivers: uses drivers
- Developer → CoreMark benchmark: runs benchmark
- Developer → Dhrystone benchmark: runs benchmark
- Developer → Architecture tests: runs tests
- Developer → ISA tests: runs tests
- Developer → Debug tests: runs debug tests
- Developer → Simulation tests: runs simulations
- Developer → Trace parser: parses trace
- Spike simulator → Trace parser: produces log
- Developer → OpenLane helper: invokes helper
- KIZIL CPU → Pipeline core: includes
- KIZIL CPU → System design: described by