# intel/fpga-npu architecture

> Architecture diagram of the GitHub repository intel/fpga-npu, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-30). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/intel/fpga-npu
- Repository: https://github.com/intel/fpga-npu

## Overview

This repository implements an FPGA-oriented neural processing unit for low-latency inference, with software tooling to express workloads and a cycle-level C++ simulator. The main user path is a Keras model or workload being translated into NPU operations, then modeled by the simulator; the README also describes programming deployed FPGA hardware. The tree includes a PCIe kernel and user API as a separate access subsystem. Evidence is limited to the README, excerpts, and SOURCE INDEX references, so unsampled implementation links are omitted or marked unverified.

Main entry points: [`simulator/src/datapath.cpp`](https://github.com/intel/fpga-npu/blob/main/simulator/src/datapath.cpp) (NPU datapath), [`compiler/compiler.py`](https://github.com/intel/fpga-npu/blob/main/compiler/compiler.py) (NPU compiler), [`compiler/npu_layers.py`](https://github.com/intel/fpga-npu/blob/main/compiler/npu_layers.py) (NPU layers), [`simulator/main/npu_sim.cpp`](https://github.com/intel/fpga-npu/blob/main/simulator/main/npu_sim.cpp) (Simulator entry)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_software["Workload software"]
  node_keras["Keras model"]
  node_layers["NPU layers<br/>[npu_layers.py]"]
  node_compiler["NPU compiler<br/>[compiler.py]"]
  node_driver["Compiler driver<br/>[driver.py]"]
  node_fsim["Functional simulator<br/>[fsim.py]"]
  node_workloads["Example workloads"]
end

subgraph group_sim["NPU simulator"]
  node_sim_entry["Simulator entry<br/>[npu_sim.cpp]"]
  node_loader["Instruction loader<br/>[loader.cpp]"]
  node_decoder["Instruction decoder<br/>[decoder.cpp]"]
  node_datapath["NPU datapath<br/>[datapath.cpp]"]
  node_mvu["Matrix-vector unit<br/>[mvu.cpp]"]
  node_tile["MVU tiles<br/>[tile.cpp]"]
  node_dpe["Processing elements<br/>[dpe.cpp]"]
  node_evrf["Element VRF<br/>[evrf.cpp]"]
  node_mfu["Vector functions<br/>[mfu.cpp]"]
  node_channels["Pipeline channels<br/>[channel.cpp]"]
end

subgraph group_pcie["PCIe access"]
  node_pcie_user["User PCIe API"]
  node_pcie_kernel["PCIe kernel driver"]
end

node_user(("AI developer"))

node_user -->|"defines model"| node_keras
node_user -->|"programs workloads"| node_compiler
node_keras -->|"compiles model"| node_layers
node_layers -->|"builds operations"| node_compiler
node_driver -->|"imports"| node_compiler
node_driver -->|"imports"| node_layers
node_compiler -->|"uses model"| node_fsim
node_workloads -->|"uses compiler"| node_compiler
node_workloads -->|"uses layers"| node_layers
node_sim_entry -.->|"loads instructions"| node_loader
node_sim_entry -.->|"runs decoder"| node_decoder
node_sim_entry -.->|"runs datapath"| node_datapath
node_datapath -->|"connects stage"| node_mvu
node_datapath -->|"connects stage"| node_evrf
node_datapath -->|"connects stages"| node_mfu
node_datapath -->|"connects stage"| node_loader
node_datapath -->|"transfers data"| node_channels
node_mvu -->|"uses tiles"| node_tile
node_tile -->|"contains compute"| node_dpe
node_user -.->|"accesses device"| node_pcie_user
node_pcie_user -.->|"device I/O"| node_pcie_kernel

click node_layers "https://github.com/intel/fpga-npu/blob/main/compiler/npu_layers.py"
click node_compiler "https://github.com/intel/fpga-npu/blob/main/compiler/compiler.py"
click node_driver "https://github.com/intel/fpga-npu/blob/main/compiler/driver.py"
click node_fsim "https://github.com/intel/fpga-npu/blob/main/compiler/fsim.py"
click node_workloads "https://github.com/intel/fpga-npu/tree/main/scripts/workloads"
click node_sim_entry "https://github.com/intel/fpga-npu/blob/main/simulator/main/npu_sim.cpp"
click node_loader "https://github.com/intel/fpga-npu/blob/main/simulator/src/loader.cpp"
click node_decoder "https://github.com/intel/fpga-npu/blob/main/simulator/src/decoder.cpp"
click node_datapath "https://github.com/intel/fpga-npu/blob/main/simulator/src/datapath.cpp"
click node_mvu "https://github.com/intel/fpga-npu/blob/main/simulator/src/mvu.cpp"
click node_tile "https://github.com/intel/fpga-npu/blob/main/simulator/src/tile.cpp"
click node_dpe "https://github.com/intel/fpga-npu/blob/main/simulator/src/dpe.cpp"
click node_evrf "https://github.com/intel/fpga-npu/blob/main/simulator/src/evrf.cpp"
click node_mfu "https://github.com/intel/fpga-npu/blob/main/simulator/src/mfu.cpp"
click node_channels "https://github.com/intel/fpga-npu/blob/main/simulator/src/channel.cpp"
click node_pcie_user "https://github.com/intel/fpga-npu/blob/main/patch/user/intel_fpga_pcie_api_linux.cpp"
click node_pcie_kernel "https://github.com/intel/fpga-npu/tree/main/patch/kernel"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_keras,node_layers,node_compiler,node_driver,node_fsim,node_workloads toneBlue
class node_sim_entry,node_loader,node_decoder,node_datapath,node_mvu,node_tile,node_dpe,node_evrf,node_mfu,node_channels toneAmber
class node_pcie_user,node_pcie_kernel toneMint
class node_user toneIndigo
```

## Components

### Workload software

- **Keras model**
- [NPU layers](https://github.com/intel/fpga-npu/blob/main/compiler/npu_layers.py): `compiler/npu_layers.py`
- [NPU compiler](https://github.com/intel/fpga-npu/blob/main/compiler/compiler.py): `compiler/compiler.py`
- [Compiler driver](https://github.com/intel/fpga-npu/blob/main/compiler/driver.py): `compiler/driver.py`
- [Functional simulator](https://github.com/intel/fpga-npu/blob/main/compiler/fsim.py): `compiler/fsim.py`
- [Example workloads](https://github.com/intel/fpga-npu/tree/main/scripts/workloads): `scripts/workloads`

### NPU simulator

- [Simulator entry](https://github.com/intel/fpga-npu/blob/main/simulator/main/npu_sim.cpp): `simulator/main/npu_sim.cpp`
- [Instruction loader](https://github.com/intel/fpga-npu/blob/main/simulator/src/loader.cpp): `simulator/src/loader.cpp`
- [Instruction decoder](https://github.com/intel/fpga-npu/blob/main/simulator/src/decoder.cpp): `simulator/src/decoder.cpp`
- [NPU datapath](https://github.com/intel/fpga-npu/blob/main/simulator/src/datapath.cpp): `simulator/src/datapath.cpp`
- [Matrix-vector unit](https://github.com/intel/fpga-npu/blob/main/simulator/src/mvu.cpp): `simulator/src/mvu.cpp`
- [MVU tiles](https://github.com/intel/fpga-npu/blob/main/simulator/src/tile.cpp): `simulator/src/tile.cpp`
- [Processing elements](https://github.com/intel/fpga-npu/blob/main/simulator/src/dpe.cpp): `simulator/src/dpe.cpp`
- [Element VRF](https://github.com/intel/fpga-npu/blob/main/simulator/src/evrf.cpp): `simulator/src/evrf.cpp`
- [Vector functions](https://github.com/intel/fpga-npu/blob/main/simulator/src/mfu.cpp): `simulator/src/mfu.cpp`
- [Pipeline channels](https://github.com/intel/fpga-npu/blob/main/simulator/src/channel.cpp): `simulator/src/channel.cpp`

### PCIe access

- [User PCIe API](https://github.com/intel/fpga-npu/blob/main/patch/user/intel_fpga_pcie_api_linux.cpp): `patch/user/intel_fpga_pcie_api_linux.cpp`
- [PCIe kernel driver](https://github.com/intel/fpga-npu/tree/main/patch/kernel): `patch/kernel`

### Other components

- **AI developer**

## Connections

- AI developer → Keras model: defines model
- AI developer → NPU compiler: programs workloads
- Keras model → NPU layers: compiles model (evidence: `compiler/npu_layers.py`)
- NPU layers → NPU compiler: builds operations (evidence: `compiler/npu_layers.py`)
- Compiler driver → NPU compiler: imports (evidence: `compiler/driver.py`)
- Compiler driver → NPU layers: imports (evidence: `compiler/driver.py`)
- NPU compiler → Functional simulator: uses model (evidence: `compiler/compiler.py`)
- Example workloads → NPU compiler: uses compiler (evidence: `scripts/workloads/18_mlp3_1024_512_256_256.py`)
- Example workloads → NPU layers: uses layers (evidence: `scripts/workloads/18_mlp3_1024_512_256_256.py`)
- Simulator entry → Instruction loader: loads instructions
- Simulator entry → Instruction decoder: runs decoder
- Simulator entry → NPU datapath: runs datapath
- NPU datapath → Matrix-vector unit: connects stage
- NPU datapath → Element VRF: connects stage
- NPU datapath → Vector functions: connects stages
- NPU datapath → Instruction loader: connects stage
- NPU datapath → Pipeline channels: transfers data
- Matrix-vector unit → MVU tiles: uses tiles
- MVU tiles → Processing elements: contains compute
- AI developer → User PCIe API: accesses device
- User PCIe API → PCIe kernel driver: device I/O