How huyhuy-bit/rv32i-datapath-singlecycle works
This repository is a single-cycle RV32I processor: each cycle the core fetches an instruction, decodes it, executes it, optionally accesses data memory, writes back a result, and selects the next PC. The README documents the top-level wiring and block responsibilities; RTL excerpts were not provided, so the connections below rely on that documentation rather than inspected implementation details.
Main entry points: cpu.sv CPU core · pc.sv Program counter · instr_mem.sv Instruction memory · control.sv Instruction decoder
Components 9
Fetch and decode
- Program counter
pc.sv - Instruction memory
instr_mem.sv - Instruction decoder
control.sv
Execute and control flow
- CPU core
cpu.sv - Immediate generator
imm_gen.sv - Arithmetic logic unit
alu.sv - Branch comparator
branch_unit.sv
Processor state and memory
- Register file
reg_file.sv - Data memory
data_mem.sv
Connections 9
- CPU core → Program counter: updates
README.md - Program counter → CPU core: provides PC
README.md - CPU core → Instruction memory: fetches instruction
README.md - CPU core → Instruction decoder: decodes instruction
README.md - CPU core → Register file: reads and writes
README.md - CPU core → Immediate generator: generates immediate
README.md - CPU core → Arithmetic logic unit: executes operation
README.md - CPU core → Branch comparator: evaluates branch
README.md - CPU core → Data memory: accesses data
README.md