# huyhuy-bit/rv32i-datapath-singlecycle architecture

> Architecture diagram of the GitHub repository huyhuy-bit/rv32i-datapath-singlecycle, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-10-01). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/huyhuy-bit/rv32i-datapath-singlecycle
- Repository: https://github.com/huyhuy-bit/rv32i-datapath-singlecycle

## Overview

This repository is a single-cycle RV32I processor: each cycle the core fetches an instruction, decodes it, executes it, optionally accesses data memory, writes back a result, and selects the next PC. The README documents the top-level wiring and block responsibilities; RTL excerpts were not provided, so the connections below rely on that documentation rather than inspected implementation details.

Main entry points: [`cpu.sv`](https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/cpu.sv) (CPU core), [`pc.sv`](https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/pc.sv) (Program counter), [`instr_mem.sv`](https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/instr_mem.sv) (Instruction memory), [`control.sv`](https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/control.sv) (Instruction decoder)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_fetch_decode["Fetch and decode"]
  node_pc["Program counter<br/>[pc.sv]"]
  node_instr_mem[("Instruction memory<br/>[instr_mem.sv]")]
  node_control["Instruction decoder<br/>[control.sv]"]
end

subgraph group_execute["Execute and control flow"]
  node_cpu["CPU core<br/>[cpu.sv]"]
  node_imm_gen["Immediate generator<br/>[imm_gen.sv]"]
  node_alu["Arithmetic logic unit<br/>[alu.sv]"]
  node_branch_unit["Branch comparator<br/>[branch_unit.sv]"]
end

subgraph group_state["Processor state and memory"]
  node_reg_file[("Register file<br/>[reg_file.sv]")]
  node_data_mem[("Data memory<br/>[data_mem.sv]")]
end

node_cpu -->|"updates"| node_pc
node_pc -->|"provides PC"| node_cpu
node_cpu -->|"fetches instruction"| node_instr_mem
node_cpu -->|"decodes instruction"| node_control
node_cpu -->|"reads and writes"| node_reg_file
node_cpu -->|"generates immediate"| node_imm_gen
node_cpu -->|"executes operation"| node_alu
node_cpu -->|"evaluates branch"| node_branch_unit
node_cpu -->|"accesses data"| node_data_mem

click node_cpu "https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/cpu.sv"
click node_pc "https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/pc.sv"
click node_instr_mem "https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/instr_mem.sv"
click node_control "https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/control.sv"
click node_imm_gen "https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/imm_gen.sv"
click node_reg_file "https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/reg_file.sv"
click node_alu "https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/alu.sv"
click node_branch_unit "https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/branch_unit.sv"
click node_data_mem "https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/data_mem.sv"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_pc,node_instr_mem,node_control toneBlue
class node_cpu,node_imm_gen,node_alu,node_branch_unit toneAmber
class node_reg_file,node_data_mem toneMint
```

## Components

### Fetch and decode

- [Program counter](https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/pc.sv): `pc.sv`
- [Instruction memory](https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/instr_mem.sv): `instr_mem.sv`
- [Instruction decoder](https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/control.sv): `control.sv`

### Execute and control flow

- [CPU core](https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/cpu.sv): `cpu.sv`
- [Immediate generator](https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/imm_gen.sv): `imm_gen.sv`
- [Arithmetic logic unit](https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/alu.sv): `alu.sv`
- [Branch comparator](https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/branch_unit.sv): `branch_unit.sv`

### Processor state and memory

- [Register file](https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/reg_file.sv): `reg_file.sv`
- [Data memory](https://github.com/huyhuy-bit/rv32i-datapath-singlecycle/blob/main/data_mem.sv): `data_mem.sv`

## Connections

- CPU core → Program counter: updates (evidence: `README.md`)
- Program counter → CPU core: provides PC (evidence: `README.md`)
- CPU core → Instruction memory: fetches instruction (evidence: `README.md`)
- CPU core → Instruction decoder: decodes instruction (evidence: `README.md`)
- CPU core → Register file: reads and writes (evidence: `README.md`)
- CPU core → Immediate generator: generates immediate (evidence: `README.md`)
- CPU core → Arithmetic logic unit: executes operation (evidence: `README.md`)
- CPU core → Branch comparator: evaluates branch (evidence: `README.md`)
- CPU core → Data memory: accesses data (evidence: `README.md`)