harshithajm-vlsi/rsic-5-stage-pipeline

Purpose and Top-Level Integration

This repository implements a Verilog RISC-V processor organized as a five-stage pipeline for Vivado/Xilinx simulation or synthesis. The primary integration point is processor top.v; its project container is 5_stage_risc_recovery.xpr.

Instruction Fetch (IF)

Fetch owns program-counter sequencing and instruction retrieval:

• program counter.v holds the current PC.

• PC adder.v computes sequential next addresses.

• Instruction memeory.v supplies instructions addressed by the PC.

• IF Stage.v likely composes these fetch-side functions.

• if_id_register.v transfers fetched instruction and PC context into decode.

Decode, Register Read, and Control

The decode boundary interprets the IF/ID instruction and prepares execution inputs:

• register file.v provides architectural register reads and receives write-back updates.

• control unit.v derives pipeline control signals from instruction fields.

• immedate generator.v produces instruction-format-dependent immediates.

• id_ex_register.v captures decoded operands, immediate values, register identifiers, and control signals.

Execute and ALU Control

Execution selects the ALU operation and computes arithmetic, logical, or address results:

• ALU.v is the main datapath compute unit.

• alu control unit.v refines the high-level decode control into an ALU operation.

• id_ex_register.v is the input boundary to execute.

• ex-mem_register.v captures ALU results, store data, destination register, and memory/write-back controls.

Memory Access

The memory stage consumes EX/MEM state and performs data-memory transactions:

• Data Memeory.v implements the load/store memory interface or storage model.

• ex-mem_register.v isolates execute from memory timing.

• mem_wb_register.v captures memory read data and forwarded ALU results for retirement.

Instruction memory and data memory are separate modules (Instruction memeory.v, Data Memeory.v), establishing a Harvard-style pipeline boundary.

Write Back and Architectural State

Retirement selects the value written to the register file:

• Write Back.v chooses between memory data and execution results.

• mem_wb_register.v supplies final-stage state.

• register file.v is the principal architectural state updated by the pipeline.

Hazard Recovery and Forwarding

Pipeline correctness logic handles data dependencies:

• hazard detection unit.v detects hazards that require fetch/decode stalling or pipeline bubbling, especially load-use dependencies.

• forwardimg unit.v selects bypass sources from later pipeline stages to avoid unnecessary stalls.

• These controls cross the decode/execute and execute/memory boundaries represented by if_id_register.v, id_ex_register.v, and ex-mem_register.v.

Runtime and Infrastructure

The design is RTL Verilog, intended for Xilinx Vivado as indicated by 5_stage_risc_recovery.xpr. There are no application services, network interfaces, or external runtime dependencies evident in the repository; execution is hardware-clock-driven simulation or synthesized FPGA logic.