# harshithajm-vlsi/rsic-5-stage-pipeline architecture

> Architecture diagram of the GitHub repository harshithajm-vlsi/rsic-5-stage-pipeline, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-08-14). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/harshithajm-vlsi/rsic-5-stage-pipeline
- Repository: https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline

## Overview

#### Purpose and Top-Level Integration
This repository implements a Verilog RISC-V processor organized as a five-stage pipeline for Vivado/Xilinx simulation or synthesis. The primary integration point is `processor top.v`; its project container is `5_stage_risc_recovery.xpr`.

#### Instruction Fetch (IF)
Fetch owns program-counter sequencing and instruction retrieval:
- `program counter.v` holds the current PC.
- `PC adder.v` computes sequential next addresses.
- `Instruction memeory.v` supplies instructions addressed by the PC.
- `IF Stage.v` likely composes these fetch-side functions.
- `if_id_register.v` transfers fetched instruction and PC context into decode.

#### Decode, Register Read, and Control
The decode boundary interprets the IF/ID instruction and prepares execution inputs:
- `register file.v` provides architectural register reads and receives write-back updates.
- `control unit.v` derives pipeline control signals from instruction fields.
- `immedate generator.v` produces instruction-format-dependent immediates.
- `id_ex_register.v` captures decoded operands, immediate values, register identifiers, and control signals.

#### Execute and ALU Control
Execution selects the ALU operation and computes arithmetic, logical, or address results:
- `ALU.v` is the main datapath compute unit.
- `alu control unit.v` refines the high-level decode control into an ALU operation.
- `id_ex_register.v` is the input boundary to execute.
- `ex-mem_register.v` captures ALU results, store data, destination register, and memory/write-back controls.

#### Memory Access
The memory stage consumes EX/MEM state and performs data-memory transactions:
- `Data Memeory.v` implements the load/store memory interface or storage model.
- `ex-mem_register.v` isolates execute from memory timing.
- `mem_wb_register.v` captures memory read data and forwarded ALU results for retirement.

Instruction memory and data memory are separate modules (`Instruction memeory.v`, `Data Memeory.v`), establishing a Harvard-style pipeline boundary.

#### Write Back and Architectural State
Retirement selects the value written to the register file:
- `Write Back.v` chooses between memory data and execution results.
- `mem_wb_register.v` supplies final-stage state.
- `register file.v` is the principal architectural state updated by the pipeline.

#### Hazard Recovery and Forwarding
Pipeline correctness logic handles data dependencies:
- `hazard detection unit.v` detects hazards that require fetch/decode stalling or pipeline bubbling, especially load-use dependencies.
- `forwardimg unit.v` selects bypass sources from later pipeline stages to avoid unnecessary stalls.
- These controls cross the decode/execute and execute/memory boundaries represented by `if_id_register.v`, `id_ex_register.v`, and `ex-mem_register.v`.

#### Runtime and Infrastructure
The design is RTL Verilog, intended for Xilinx Vivado as indicated by `5_stage_risc_recovery.xpr`. There are no application services, network interfaces, or external runtime dependencies evident in the repository; execution is hardware-clock-driven simulation or synthesized FPGA logic.

Main entry points: [`id_ex_register.v`](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/id_ex_register.v) (ID/EX Register), [`if_id_register.v`](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/if_id_register.v) (IF/ID Register), [`ex-mem_register.v`](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/ex-mem_register.v) (EX/MEM Register), [`program counter.v`](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/program%20counter.v) (Program Counter)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_fetch["Instruction Fetch"]
  node_if_stage["IF Stage<br/>fetch composition<br/>[IF Stage.v]"]
  node_pc["Program Counter<br/>PC state<br/>[program counter.v]"]
  node_pc_adder["PC Adder<br/>next-PC logic<br/>[PC adder.v]"]
  node_instruction_memory[("Instruction Memory<br/>instruction storage")]
  node_if_id["IF/ID Register<br/>pipeline register<br/>[if_id_register.v]"]
end

subgraph group_decode["Decode &amp; Read"]
  node_register_file[("Register File<br/>architectural state<br/>[register file.v]")]
  node_control["Control Unit<br/>instruction decode<br/>[control unit.v]"]
  node_immediate["Immediate Generator<br/>operand decode"]
  node_id_ex["ID/EX Register<br/>pipeline register<br/>[id_ex_register.v]"]
end

subgraph group_execute["Execute"]
  node_alu_control["ALU Control<br/>operation decode<br/>[alu control unit.v]"]
  node_alu["ALU<br/>datapath compute<br/>[ALU.v]"]
  node_ex_mem["EX/MEM Register<br/>pipeline register<br/>[ex-mem_register.v]"]
end

subgraph group_memory["Memory &amp; Write Back"]
  node_data_memory[("Data Memory<br/>load/store storage<br/>[Data Memeory.v]")]
  node_mem_wb["MEM/WB Register<br/>pipeline register<br/>[mem_wb_register.v]"]
  node_write_back["Write Back<br/>retirement mux<br/>[Write Back.v]"]
end

subgraph group_recovery["Hazard Recovery"]
  node_hazard{{"Hazard Detection<br/>stall and bubble control"}}
  node_forwarding{{"Forwarding Unit<br/>bypass control<br/>[forwardimg unit.v]"}}
end

node_project["Vivado Project<br/>Xilinx project"]
node_top["Processor Top<br/>RTL integration<br/>[processor top.v]"]

node_project -->|"contains"| node_top
node_top -->|"fetch"| node_if_stage
node_if_stage -->|"updates"| node_pc
node_pc -->|"PC"| node_pc_adder
node_pc_adder -->|"next PC"| node_pc
node_pc -->|"address"| node_instruction_memory
node_instruction_memory -->|"instruction"| node_if_id
node_if_id -->|"instruction fields"| node_control
node_if_id -->|"instruction fields"| node_immediate
node_if_id -->|"source registers"| node_register_file
node_register_file -->|"read operands"| node_id_ex
node_control -->|"controls"| node_id_ex
node_immediate -->|"immediate"| node_id_ex
node_id_ex -->|"ALU decode"| node_alu_control
node_id_ex -->|"operands"| node_alu
node_alu_control -->|"operation"| node_alu
node_alu -->|"result"| node_ex_mem
node_id_ex -->|"store data and controls"| node_ex_mem
node_ex_mem -->|"address, store data"| node_data_memory
node_ex_mem -->|"ALU result and controls"| node_mem_wb
node_data_memory -->|"load data"| node_mem_wb
node_mem_wb -->|"retirement inputs"| node_write_back
node_write_back -->|"register update"| node_register_file
node_if_id -.->|"decode sources"| node_hazard
node_id_ex -.->|"load destination"| node_hazard
node_hazard -.->|"stall PC/fetch"| node_if_stage
node_hazard -.->|"bubble control"| node_id_ex
node_id_ex -.->|"source registers"| node_forwarding
node_ex_mem -.->|"bypass source"| node_forwarding
node_mem_wb -.->|"bypass source"| node_forwarding
node_forwarding -.->|"operand select"| node_alu

click node_project "https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/5_stage_risc_recovery.xpr"
click node_top "https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/processor%20top.v"
click node_if_stage "https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/IF%20Stage.v"
click node_pc "https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/program%20counter.v"
click node_pc_adder "https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/PC%20adder.v"
click node_instruction_memory "https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/Instruction%20memeory.v"
click node_if_id "https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/if_id_register.v"
click node_register_file "https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/register%20file.v"
click node_control "https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/control%20unit.v"
click node_immediate "https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/immedate%20generator.v"
click node_id_ex "https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/id_ex_register.v"
click node_alu_control "https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/alu%20control%20unit.v"
click node_alu "https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/ALU.v"
click node_ex_mem "https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/ex-mem_register.v"
click node_data_memory "https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/Data%20Memeory.v"
click node_mem_wb "https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/mem_wb_register.v"
click node_write_back "https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/Write%20Back.v"
click node_hazard "https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/hazard%20detection%20unit.v"
click node_forwarding "https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/forwardimg%20unit.v"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_if_stage,node_pc,node_pc_adder,node_instruction_memory,node_if_id toneBlue
class node_register_file,node_control,node_immediate,node_id_ex toneAmber
class node_alu_control,node_alu,node_ex_mem toneMint
class node_data_memory,node_mem_wb,node_write_back toneRose
class node_hazard,node_forwarding toneIndigo
class node_project,node_top toneNeutral
```

## Components

### Instruction Fetch

- [IF Stage](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/IF%20Stage.v): fetch composition · `IF Stage.v`
- [Program Counter](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/program%20counter.v): PC state · `program counter.v`
- [PC Adder](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/PC%20adder.v): next-PC logic · `PC adder.v`
- [Instruction Memory](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/Instruction%20memeory.v): instruction storage · `Instruction memeory.v`
- [IF/ID Register](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/if_id_register.v): pipeline register · `if_id_register.v`

### Decode & Read

- [Register File](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/register%20file.v): architectural state · Supplies decode operands and receives write-back results. · `register file.v`
- [Control Unit](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/control%20unit.v): instruction decode · `control unit.v`
- [Immediate Generator](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/immedate%20generator.v): operand decode · `immedate generator.v`
- [ID/EX Register](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/id_ex_register.v): pipeline register · `id_ex_register.v`

### Execute

- [ALU Control](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/alu%20control%20unit.v): operation decode · `alu control unit.v`
- [ALU](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/ALU.v): datapath compute · `ALU.v`
- [EX/MEM Register](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/ex-mem_register.v): pipeline register · `ex-mem_register.v`

### Memory & Write Back

- [Data Memory](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/Data%20Memeory.v): load/store storage · `Data Memeory.v`
- [MEM/WB Register](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/mem_wb_register.v): pipeline register · `mem_wb_register.v`
- [Write Back](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/Write%20Back.v): retirement mux · `Write Back.v`

### Hazard Recovery

- [Hazard Detection](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/hazard%20detection%20unit.v): stall and bubble control · Detects load-use dependencies. · `hazard detection unit.v`
- [Forwarding Unit](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/forwardimg%20unit.v): bypass control · `forwardimg unit.v`

### Other components

- [Vivado Project](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/5_stage_risc_recovery.xpr): Xilinx project · `5_stage_risc_recovery.xpr`
- [Processor Top](https://github.com/harshithajm-vlsi/rsic-5-stage-pipeline/blob/main/processor%20top.v): RTL integration · Integrates the five-stage RISC-V pipeline. · `processor top.v`

## Connections

- Vivado Project → Processor Top: contains
- Processor Top → IF Stage: fetch
- IF Stage → Program Counter: updates
- Program Counter → PC Adder: PC
- PC Adder → Program Counter: next PC
- Program Counter → Instruction Memory: address
- Instruction Memory → IF/ID Register: instruction
- IF/ID Register → Control Unit: instruction fields
- IF/ID Register → Immediate Generator: instruction fields
- IF/ID Register → Register File: source registers
- Register File → ID/EX Register: read operands
- Control Unit → ID/EX Register: controls
- Immediate Generator → ID/EX Register: immediate
- ID/EX Register → ALU Control: ALU decode
- ID/EX Register → ALU: operands
- ALU Control → ALU: operation
- ALU → EX/MEM Register: result
- ID/EX Register → EX/MEM Register: store data and controls
- EX/MEM Register → Data Memory: address, store data
- EX/MEM Register → MEM/WB Register: ALU result and controls
- Data Memory → MEM/WB Register: load data
- MEM/WB Register → Write Back: retirement inputs
- Write Back → Register File: register update
- IF/ID Register → Hazard Detection: decode sources
- ID/EX Register → Hazard Detection: load destination
- Hazard Detection → IF Stage: stall PC/fetch
- Hazard Detection → ID/EX Register: bubble control
- ID/EX Register → Forwarding Unit: source registers
- EX/MEM Register → Forwarding Unit: bypass source
- MEM/WB Register → Forwarding Unit: bypass source
- Forwarding Unit → ALU: operand select