# gourav-ctrl/risc-v architecture

> Architecture diagram of the GitHub repository gourav-ctrl/risc-v, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-27). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/gourav-ctrl/risc-v
- Repository: https://github.com/gourav-ctrl/risc-v

## Overview

This repository appears to implement a RISC-V processor: its RTL filenames identify fetch, control, execution, and state modules. No README or source excerpts are available, so their wiring and the precise instruction-to-result flow cannot be verified; the graph therefore shows the named components without asserting connections. The testbench is excluded.

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_core["Core"]
  node_top["RISC-V top<br/>[top_riscv.v]"]
end

subgraph group_control["Instruction control"]
  node_fetch["Instruction fetch"]
  node_decode["Instruction memory"]
  node_control_unit["Control unit<br/>[control_unit.v]"]
  node_immediate["Immediate generator<br/>[imm_gen.v]"]
end

subgraph group_execution["Execution and state"]
  node_datapath["Datapath<br/>[data_path.v]"]
  node_alu["ALU<br/>[alu.v]"]
  node_registers[("Register file<br/>[register_file.v]")]
  node_data_memory[("Data memory<br/>[data_memory.v]")]
end

click node_top "https://github.com/gourav-ctrl/risc-v/blob/main/top_riscv.v"
click node_fetch "https://github.com/gourav-ctrl/risc-v/blob/main/instruction_fetch_unit.v"
click node_decode "https://github.com/gourav-ctrl/risc-v/blob/main/INSTRUCTION_MEMORY.v"
click node_control_unit "https://github.com/gourav-ctrl/risc-v/blob/main/control_unit.v"
click node_immediate "https://github.com/gourav-ctrl/risc-v/blob/main/imm_gen.v"
click node_datapath "https://github.com/gourav-ctrl/risc-v/blob/main/data_path.v"
click node_alu "https://github.com/gourav-ctrl/risc-v/blob/main/alu.v"
click node_registers "https://github.com/gourav-ctrl/risc-v/blob/main/register_file.v"
click node_data_memory "https://github.com/gourav-ctrl/risc-v/blob/main/data_memory.v"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_top toneBlue
class node_fetch,node_decode,node_control_unit,node_immediate toneAmber
class node_datapath,node_alu,node_registers,node_data_memory toneMint
```

## Components

### Core

- [RISC-V top](https://github.com/gourav-ctrl/risc-v/blob/main/top_riscv.v): `top_riscv.v`

### Instruction control

- [Instruction fetch](https://github.com/gourav-ctrl/risc-v/blob/main/instruction_fetch_unit.v): `instruction_fetch_unit.v`
- [Instruction memory](https://github.com/gourav-ctrl/risc-v/blob/main/INSTRUCTION_MEMORY.v): `INSTRUCTION_MEMORY.v`
- [Control unit](https://github.com/gourav-ctrl/risc-v/blob/main/control_unit.v): `control_unit.v`
- [Immediate generator](https://github.com/gourav-ctrl/risc-v/blob/main/imm_gen.v): `imm_gen.v`

### Execution and state

- [Datapath](https://github.com/gourav-ctrl/risc-v/blob/main/data_path.v): `data_path.v`
- [ALU](https://github.com/gourav-ctrl/risc-v/blob/main/alu.v): `alu.v`
- [Register file](https://github.com/gourav-ctrl/risc-v/blob/main/register_file.v): `register_file.v`
- [Data memory](https://github.com/gourav-ctrl/risc-v/blob/main/data_memory.v): `data_memory.v`