How gicm-udea/custom_ip_cores_lib works
This repository is a reusable FPGA IP-core library, not a single end-user application. The README documents adding the IP repository to Vivado and points users to separate project repositories for reference designs. The tree identifies three cores; source excerpts are unavailable, so internal wiring and detailed user-to-result flows cannot be verified.
Main entry points: cdcc.vhd CDCC IP · oscilloscope.vhd Oscilloscope IP · pulse_gen_ip.v Pulse Generator IP
Components 17
CDCC Core
- CDCC IP
ip/cdcc/src/cdcc.vhd
Oscilloscope Core
- Oscilloscope IP
ip/oscilloscope/src/oscilloscope.vhd - Axis Ring Buffer
ip/oscilloscope/src/axis_ring_buffer.vhd - Decimator
ip/oscilloscope/src/decimator_v2.vhd - Sync Mux
ip/oscilloscope/src/sync_mux.vhd - Threshold
ip/oscilloscope/src/threshold_v2.vhd - Trigger Write Enable
ip/oscilloscope/src/trig_wr_enabled_v2.vhd
Pulse Generation Core
- Pulse Generator IP
ip/rnpg/src/pulse_gen_ip.v - Xoshiro PRNG
ip/rnpg/src/Xoshiro32bit.vhd - Bernoulli Trial
ip/rnpg/src/bernoulli_trial.vhd - Random Channel
ip/rnpg/src/rand_to_channel.vhd - Pileup Manager
ip/rnpg/src/pileup_manager.vhd - Pileup Adder
ip/rnpg/src/pileup_adder.vhd - DAC Ramp
ip/rnpg/src/dac_ramp.vhd - Signal Send
ip/rnpg/src/signal_send.vhd
Other components
- FPGA Designer
- Vivado
Connections 4
- FPGA Designer → Vivado: adds IP repository
- Vivado → CDCC IP: integrates IP
- Vivado → Oscilloscope IP: integrates IP
- Vivado → Pulse Generator IP: integrates IP