# gicm-udea/custom_ip_cores_lib architecture

> Architecture diagram of the GitHub repository gicm-udea/custom_ip_cores_lib, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-25). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/gicm-udea/custom_ip_cores_lib
- Repository: https://github.com/gicm-udea/custom_ip_cores_lib

## Overview

This repository is a reusable FPGA IP-core library, not a single end-user application. The README documents adding the IP repository to Vivado and points users to separate project repositories for reference designs. The tree identifies three cores; source excerpts are unavailable, so internal wiring and detailed user-to-result flows cannot be verified.

Main entry points: [`ip/cdcc/src/cdcc.vhd`](https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/cdcc/src/cdcc.vhd) (CDCC IP), [`ip/oscilloscope/src/oscilloscope.vhd`](https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/oscilloscope/src/oscilloscope.vhd) (Oscilloscope IP), [`ip/rnpg/src/pulse_gen_ip.v`](https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/rnpg/src/pulse_gen_ip.v) (Pulse Generator IP)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_cdcc["CDCC Core"]
  node_cdcc_core["CDCC IP<br/>[cdcc.vhd]"]
end

subgraph group_scope["Oscilloscope Core"]
  node_scope_core["Oscilloscope IP<br/>[oscilloscope.vhd]"]
  node_scope_buffer["Axis Ring Buffer"]
  node_scope_decimator["Decimator<br/>[decimator_v2.vhd]"]
  node_scope_mux["Sync Mux<br/>[sync_mux.vhd]"]
  node_scope_threshold["Threshold<br/>[threshold_v2.vhd]"]
  node_scope_trigger["Trigger Write Enable"]
end

subgraph group_rnpg["Pulse Generation Core"]
  node_rnpg_core["Pulse Generator IP<br/>[pulse_gen_ip.v]"]
  node_rnpg_prng["Xoshiro PRNG<br/>[Xoshiro32bit.vhd]"]
  node_rnpg_bernoulli["Bernoulli Trial"]
  node_rnpg_channel["Random Channel"]
  node_rnpg_pileup_manager["Pileup Manager<br/>[pileup_manager.vhd]"]
  node_rnpg_pileup_adder["Pileup Adder<br/>[pileup_adder.vhd]"]
  node_rnpg_dac["DAC Ramp<br/>[dac_ramp.vhd]"]
  node_rnpg_send["Signal Send<br/>[signal_send.vhd]"]
end

node_designer(("FPGA Designer"))
node_vivado["Vivado"]

node_designer -->|"adds IP repository"| node_vivado
node_vivado -->|"integrates IP"| node_cdcc_core
node_vivado -->|"integrates IP"| node_scope_core
node_vivado -->|"integrates IP"| node_rnpg_core

click node_cdcc_core "https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/cdcc/src/cdcc.vhd"
click node_scope_core "https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/oscilloscope/src/oscilloscope.vhd"
click node_scope_buffer "https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/oscilloscope/src/axis_ring_buffer.vhd"
click node_scope_decimator "https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/oscilloscope/src/decimator_v2.vhd"
click node_scope_mux "https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/oscilloscope/src/sync_mux.vhd"
click node_scope_threshold "https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/oscilloscope/src/threshold_v2.vhd"
click node_scope_trigger "https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/oscilloscope/src/trig_wr_enabled_v2.vhd"
click node_rnpg_core "https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/rnpg/src/pulse_gen_ip.v"
click node_rnpg_prng "https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/rnpg/src/Xoshiro32bit.vhd"
click node_rnpg_bernoulli "https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/rnpg/src/bernoulli_trial.vhd"
click node_rnpg_channel "https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/rnpg/src/rand_to_channel.vhd"
click node_rnpg_pileup_manager "https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/rnpg/src/pileup_manager.vhd"
click node_rnpg_pileup_adder "https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/rnpg/src/pileup_adder.vhd"
click node_rnpg_dac "https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/rnpg/src/dac_ramp.vhd"
click node_rnpg_send "https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/rnpg/src/signal_send.vhd"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_cdcc_core toneBlue
class node_scope_core,node_scope_buffer,node_scope_decimator,node_scope_mux,node_scope_threshold,node_scope_trigger toneAmber
class node_rnpg_core,node_rnpg_prng,node_rnpg_bernoulli,node_rnpg_channel,node_rnpg_pileup_manager,node_rnpg_pileup_adder,node_rnpg_dac,node_rnpg_send toneMint
class node_designer,node_vivado toneIndigo
```

## Components

### CDCC Core

- [CDCC IP](https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/cdcc/src/cdcc.vhd): `ip/cdcc/src/cdcc.vhd`

### Oscilloscope Core

- [Oscilloscope IP](https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/oscilloscope/src/oscilloscope.vhd): `ip/oscilloscope/src/oscilloscope.vhd`
- [Axis Ring Buffer](https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/oscilloscope/src/axis_ring_buffer.vhd): `ip/oscilloscope/src/axis_ring_buffer.vhd`
- [Decimator](https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/oscilloscope/src/decimator_v2.vhd): `ip/oscilloscope/src/decimator_v2.vhd`
- [Sync Mux](https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/oscilloscope/src/sync_mux.vhd): `ip/oscilloscope/src/sync_mux.vhd`
- [Threshold](https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/oscilloscope/src/threshold_v2.vhd): `ip/oscilloscope/src/threshold_v2.vhd`
- [Trigger Write Enable](https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/oscilloscope/src/trig_wr_enabled_v2.vhd): `ip/oscilloscope/src/trig_wr_enabled_v2.vhd`

### Pulse Generation Core

- [Pulse Generator IP](https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/rnpg/src/pulse_gen_ip.v): `ip/rnpg/src/pulse_gen_ip.v`
- [Xoshiro PRNG](https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/rnpg/src/Xoshiro32bit.vhd): `ip/rnpg/src/Xoshiro32bit.vhd`
- [Bernoulli Trial](https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/rnpg/src/bernoulli_trial.vhd): `ip/rnpg/src/bernoulli_trial.vhd`
- [Random Channel](https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/rnpg/src/rand_to_channel.vhd): `ip/rnpg/src/rand_to_channel.vhd`
- [Pileup Manager](https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/rnpg/src/pileup_manager.vhd): `ip/rnpg/src/pileup_manager.vhd`
- [Pileup Adder](https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/rnpg/src/pileup_adder.vhd): `ip/rnpg/src/pileup_adder.vhd`
- [DAC Ramp](https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/rnpg/src/dac_ramp.vhd): `ip/rnpg/src/dac_ramp.vhd`
- [Signal Send](https://github.com/gicm-udea/custom_ip_cores_lib/blob/main/ip/rnpg/src/signal_send.vhd): `ip/rnpg/src/signal_send.vhd`

### Other components

- **FPGA Designer**
- **Vivado**

## Connections

- FPGA Designer → Vivado: adds IP repository
- Vivado → CDCC IP: integrates IP
- Vivado → Oscilloscope IP: integrates IP
- Vivado → Pulse Generator IP: integrates IP