How fluctlight001/cpu_for_nscscc2022_single works
This is an FPGA implementation of a Nova132A-based Loongson Cup CPU. Its principal workflow is instruction execution through a pipelined processor, with instruction and data accesses serviced through cache/memory logic and an SRAM controller; the board design also exposes display and VGA peripherals. The README documents evolving pipeline, cache, SRAM-handshake, and branch-prediction capabilities across branches, so the graph represents the documented design at a high level rather than asserting one branch’s exact configuration. Source excerpts were limited to flash-model headers, so internal wiring is inferred only where supported by the README and tree.
Main entry points: mycpu_core.v CPU Core · thinpad_top.v Thinpad Top · mycpu_top.v CPU Top · sram_ctrl.v SRAM Controller
Components 19
Processor
- CPU Top
thinpad_top.srcs/sources_1/new/Nova132A/mycpu_top.v - CPU Core
thinpad_top.srcs/sources_1/new/Nova132A/mycpu_core.v - Pipeline Stages
thinpad_top.srcs/sources_1/new/Nova132A/IF.v - Control Logic
thinpad_top.srcs/sources_1/new/Nova132A/CTRL.v - ALU
thinpad_top.srcs/sources_1/new/Nova132A/lib/alu.v
Memory System
- Address Translation
thinpad_top.srcs/sources_1/new/Nova132A/lib/mmu.v - Instruction/Data Cache
thinpad_top.srcs/sources_1/new/Nova132A/cache.v - Uncached Access
thinpad_top.srcs/sources_1/new/Nova132A/uncache.v - Memory Bridge
thinpad_top.srcs/sources_1/new/Nova132A/bridge_1x3.v - SRAM Controller
thinpad_top.srcs/sources_1/new/sram_ctrl.v
Board I/O
- Configuration Registers
thinpad_top.srcs/sources_1/new/Nova132A/confreg.v - VGA Output
thinpad_top.srcs/sources_1/new/vga.v - Seven-Segment Display
thinpad_top.srcs/sources_1/new/SEG7_LUT.v
Platform
- Thinpad Top
thinpad_top.srcs/sources_1/new/thinpad_top.v - Clocking
thinpad_top.srcs/sources_1/new/clock_converter.v - PLL
thinpad_top.srcs/sources_1/ip/pll_example/pll_example.v - Flash Model
thinpad_top.srcs/sim_1/new/28F640P30.v
Other components
- Sample Assembly
asm/user-sample.s - SRAM
Connections 18
- Thinpad Top → Clocking: uses clocks
- Clocking → PLL: derives clocks
- Thinpad Top → CPU Top: hosts CPU
- CPU Top → CPU Core: runs core
- Sample Assembly → SRAM: loaded as program
- CPU Core → Pipeline Stages: executes pipeline
- CPU Core → Control Logic: uses control
- CPU Core → ALU: computes operations
- CPU Core → Address Translation: translates addresses
- CPU Core → Instruction/Data Cache: accesses cache
- CPU Core → Uncached Access: issues uncached access
- CPU Top → Memory Bridge: routes memory requests
- Thinpad Top → SRAM Controller: connects SRAM controller
- SRAM Controller → SRAM: reads and writes
- Thinpad Top → Configuration Registers: connects registers
- Thinpad Top → VGA Output: connects display
- Thinpad Top → Seven-Segment Display: drives display
- SRAM Controller → Flash Model: simulates flash access