# fluctlight001/cpu_for_nscscc2022_single architecture

> Architecture diagram of the GitHub repository fluctlight001/cpu_for_nscscc2022_single, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-28). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/fluctlight001/cpu_for_nscscc2022_single
- Repository: https://github.com/fluctlight001/cpu_for_nscscc2022_single

## Overview

This is an FPGA implementation of a Nova132A-based Loongson Cup CPU. Its principal workflow is instruction execution through a pipelined processor, with instruction and data accesses serviced through cache/memory logic and an SRAM controller; the board design also exposes display and VGA peripherals. The README documents evolving pipeline, cache, SRAM-handshake, and branch-prediction capabilities across branches, so the graph represents the documented design at a high level rather than asserting one branch’s exact configuration. Source excerpts were limited to flash-model headers, so internal wiring is inferred only where supported by the README and tree.

Main entry points: [`thinpad_top.srcs/sources_1/new/Nova132A/mycpu_core.v`](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/mycpu_core.v) (CPU Core), [`thinpad_top.srcs/sources_1/new/thinpad_top.v`](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/thinpad_top.v) (Thinpad Top), [`thinpad_top.srcs/sources_1/new/Nova132A/mycpu_top.v`](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/mycpu_top.v) (CPU Top), [`thinpad_top.srcs/sources_1/new/sram_ctrl.v`](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/sram_ctrl.v) (SRAM Controller)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_processor["Processor"]
  node_cpu_top["CPU Top<br/>[mycpu_top.v]"]
  node_core["CPU Core<br/>[mycpu_core.v]"]
  node_pipeline["Pipeline Stages<br/>[IF.v]"]
  node_control["Control Logic<br/>[CTRL.v]"]
  node_alu["ALU<br/>[alu.v]"]
end

subgraph group_memory["Memory System"]
  node_mmu["Address Translation<br/>[mmu.v]"]
  node_cache["Instruction/Data Cache<br/>[cache.v]"]
  node_uncache["Uncached Access<br/>[uncache.v]"]
  node_bridge["Memory Bridge<br/>[bridge_1x3.v]"]
  node_sram_ctrl["SRAM Controller<br/>[sram_ctrl.v]"]
end

subgraph group_board["Board I/O"]
  node_confreg["Configuration Registers<br/>[confreg.v]"]
  node_vga["VGA Output<br/>[vga.v]"]
  node_seg7["Seven-Segment Display<br/>[SEG7_LUT.v]"]
end

subgraph group_platform["Platform"]
  node_top["Thinpad Top<br/>[thinpad_top.v]"]
  node_clock["Clocking<br/>[clock_converter.v]"]
  node_pll["PLL<br/>[pll_example.v]"]
  node_flash_model["Flash Model<br/>[28F640P30.v]"]
end

node_program["Sample Assembly<br/>[user-sample.s]"]
node_sram[("SRAM")]

node_top -->|"uses clocks"| node_clock
node_clock -->|"derives clocks"| node_pll
node_top -->|"hosts CPU"| node_cpu_top
node_cpu_top -->|"runs core"| node_core
node_program -.->|"loaded as program"| node_sram
node_core -->|"executes pipeline"| node_pipeline
node_core -->|"uses control"| node_control
node_core -->|"computes operations"| node_alu
node_core -->|"translates addresses"| node_mmu
node_core -->|"accesses cache"| node_cache
node_core -->|"issues uncached access"| node_uncache
node_cpu_top -->|"routes memory requests"| node_bridge
node_top -->|"connects SRAM controller"| node_sram_ctrl
node_sram_ctrl -->|"reads and writes"| node_sram
node_top -->|"connects registers"| node_confreg
node_top -->|"connects display"| node_vga
node_top -->|"drives display"| node_seg7
node_sram_ctrl -.->|"simulates flash access"| node_flash_model

click node_program "https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/asm/user-sample.s"
click node_top "https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/thinpad_top.v"
click node_clock "https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/clock_converter.v"
click node_pll "https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/ip/pll_example/pll_example.v"
click node_cpu_top "https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/mycpu_top.v"
click node_core "https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/mycpu_core.v"
click node_pipeline "https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/IF.v"
click node_control "https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/CTRL.v"
click node_alu "https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/lib/alu.v"
click node_mmu "https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/lib/mmu.v"
click node_cache "https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/cache.v"
click node_uncache "https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/uncache.v"
click node_bridge "https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/bridge_1x3.v"
click node_sram_ctrl "https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/sram_ctrl.v"
click node_confreg "https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/confreg.v"
click node_vga "https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/vga.v"
click node_seg7 "https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/SEG7_LUT.v"
click node_flash_model "https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sim_1/new/28F640P30.v"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_cpu_top,node_core,node_pipeline,node_control,node_alu toneBlue
class node_mmu,node_cache,node_uncache,node_bridge,node_sram_ctrl,node_sram toneAmber
class node_confreg,node_vga,node_seg7 toneMint
class node_top,node_clock,node_pll,node_flash_model toneRose
class node_program toneTeal
```

## Components

### Processor

- [CPU Top](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/mycpu_top.v): `thinpad_top.srcs/sources_1/new/Nova132A/mycpu_top.v`
- [CPU Core](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/mycpu_core.v): `thinpad_top.srcs/sources_1/new/Nova132A/mycpu_core.v`
- [Pipeline Stages](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/IF.v): `thinpad_top.srcs/sources_1/new/Nova132A/IF.v`
- [Control Logic](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/CTRL.v): `thinpad_top.srcs/sources_1/new/Nova132A/CTRL.v`
- [ALU](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/lib/alu.v): `thinpad_top.srcs/sources_1/new/Nova132A/lib/alu.v`

### Memory System

- [Address Translation](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/lib/mmu.v): `thinpad_top.srcs/sources_1/new/Nova132A/lib/mmu.v`
- [Instruction/Data Cache](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/cache.v): `thinpad_top.srcs/sources_1/new/Nova132A/cache.v`
- [Uncached Access](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/uncache.v): `thinpad_top.srcs/sources_1/new/Nova132A/uncache.v`
- [Memory Bridge](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/bridge_1x3.v): `thinpad_top.srcs/sources_1/new/Nova132A/bridge_1x3.v`
- [SRAM Controller](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/sram_ctrl.v): `thinpad_top.srcs/sources_1/new/sram_ctrl.v`

### Board I/O

- [Configuration Registers](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/Nova132A/confreg.v): `thinpad_top.srcs/sources_1/new/Nova132A/confreg.v`
- [VGA Output](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/vga.v): `thinpad_top.srcs/sources_1/new/vga.v`
- [Seven-Segment Display](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/SEG7_LUT.v): `thinpad_top.srcs/sources_1/new/SEG7_LUT.v`

### Platform

- [Thinpad Top](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/thinpad_top.v): `thinpad_top.srcs/sources_1/new/thinpad_top.v`
- [Clocking](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/new/clock_converter.v): `thinpad_top.srcs/sources_1/new/clock_converter.v`
- [PLL](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sources_1/ip/pll_example/pll_example.v): `thinpad_top.srcs/sources_1/ip/pll_example/pll_example.v`
- [Flash Model](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/thinpad_top.srcs/sim_1/new/28F640P30.v): `thinpad_top.srcs/sim_1/new/28F640P30.v`

### Other components

- [Sample Assembly](https://github.com/fluctlight001/cpu_for_nscscc2022_single/blob/main/asm/user-sample.s): `asm/user-sample.s`
- **SRAM**

## Connections

- Thinpad Top → Clocking: uses clocks
- Clocking → PLL: derives clocks
- Thinpad Top → CPU Top: hosts CPU
- CPU Top → CPU Core: runs core
- Sample Assembly → SRAM: loaded as program
- CPU Core → Pipeline Stages: executes pipeline
- CPU Core → Control Logic: uses control
- CPU Core → ALU: computes operations
- CPU Core → Address Translation: translates addresses
- CPU Core → Instruction/Data Cache: accesses cache
- CPU Core → Uncached Access: issues uncached access
- CPU Top → Memory Bridge: routes memory requests
- Thinpad Top → SRAM Controller: connects SRAM controller
- SRAM Controller → SRAM: reads and writes
- Thinpad Top → Configuration Registers: connects registers
- Thinpad Top → VGA Output: connects display
- Thinpad Top → Seven-Segment Display: drives display
- SRAM Controller → Flash Model: simulates flash access