How deekshithag1320/100-day-verilog-challenge works
This repository is a catalog of standalone Verilog digital-logic and hardware-design modules, not a documented integrated application. Its files cover combinational logic, sequential circuits, memory, interfaces, and controllers. The file tree provides module names but no README or source excerpts, so relationships and a principal user-to-result workflow cannot be established; the graph therefore groups implementations by apparent function without asserting connections. Testbenches are omitted.
Components 34
Combinational Logic
- Add/Subtract
ADD_SUB.v - 8-bit ALU
ALU_8bit.v - AOI Logic
AOI.v - Basic Gates
BASIC_GATES.v - BCD to Seven-Segment
BCD_TO_7SEGMENT.v - BCD to Decimal
BCD_TO_DECIMAL.v - Binary to Excess-3
B_TO_E3.v - Binary to Gray
B_TO_G.v - Carry Lookahead Adder
CLA.v - Comparator 1
COMP1.v - Comparator 2
COMP2.v - 4-bit Comparator
COMP_4.v - 2-to-4 Decoder
DECODER_2_4.v - 3-to-8 Decoder
DECODER_3_8.v - 1-to-2 Demux
DEMUX_1_2.v - 1-to-4 Demux
DEMUX_1_4.v - 1-to-8 Demux
DEMUX_1_8.v - Excess-3 to Binary
E3_TO_B.v - 4-to-2 Encoder
ENCODER4_2.v - 8-to-3 Encoder
ENCODER8_3.v - Error Detection and Correction
ERROR_DETECTION_AND_CORRECTION.v - Full Adder
FA.v - Full Subtractor
FS.v - Gray to Binary
G_TO_B.v - Half Adder
HA.v - Half Subtractor
HS.v - 2-bit Multiplier
MUL2.v - 4-by-3 Multiplier
MUL43.v - 4-bit ALU
FOUR_BIT_ALU.v - 2-to-1 Mux
MUX_2_1.v - 4-to-1 Mux
MUX_4_1.v - 8-to-1 Mux
MUX_8_1.v - 4-to-2 Priority Encoder
PRIORITY_ENCODER_4_2.v - 8-to-3 Priority Encoder
PRIORITY_ENCODER_8_3.v