# deekshithag1320/100-day-verilog-challenge architecture

> Architecture diagram of the GitHub repository deekshithag1320/100-day-verilog-challenge, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-11-13). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/deekshithag1320/100-day-verilog-challenge
- Repository: https://github.com/deekshithag1320/100-day-verilog-challenge

## Overview

This repository is a catalog of standalone Verilog digital-logic and hardware-design modules, not a documented integrated application. Its files cover combinational logic, sequential circuits, memory, interfaces, and controllers. The file tree provides module names but no README or source excerpts, so relationships and a principal user-to-result workflow cannot be established; the graph therefore groups implementations by apparent function without asserting connections. Testbenches are omitted.

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_comb["Combinational Logic"]
  node_add_sub["Add/Subtract<br/>[ADD_SUB.v]"]
  node_alu8["8-bit ALU<br/>[ALU_8bit.v]"]
  node_aoi["AOI Logic<br/>[AOI.v]"]
  node_basic_gates["Basic Gates<br/>[BASIC_GATES.v]"]
  node_bcd_7seg["BCD to Seven-Segment<br/>[BCD_TO_7SEGMENT.v]"]
  node_bcd_decimal["BCD to Decimal<br/>[BCD_TO_DECIMAL.v]"]
  node_b_to_e3["Binary to Excess-3<br/>[B_TO_E3.v]"]
  node_b_to_g["Binary to Gray<br/>[B_TO_G.v]"]
  node_cla["Carry Lookahead Adder<br/>[CLA.v]"]
  node_comp1["Comparator 1<br/>[COMP1.v]"]
  node_comp2["Comparator 2<br/>[COMP2.v]"]
  node_comp4["4-bit Comparator<br/>[COMP_4.v]"]
  node_decoder24["2-to-4 Decoder<br/>[DECODER_2_4.v]"]
  node_decoder38["3-to-8 Decoder<br/>[DECODER_3_8.v]"]
  node_demux12["1-to-2 Demux<br/>[DEMUX_1_2.v]"]
  node_demux14["1-to-4 Demux<br/>[DEMUX_1_4.v]"]
  node_demux18["1-to-8 Demux<br/>[DEMUX_1_8.v]"]
  node_e3_to_b["Excess-3 to Binary<br/>[E3_TO_B.v]"]
  node_encoder42["4-to-2 Encoder<br/>[ENCODER4_2.v]"]
  node_encoder83["8-to-3 Encoder<br/>[ENCODER8_3.v]"]
  node_error_correction["Error Detection and Correction"]
  node_fa["Full Adder<br/>[FA.v]"]
  node_fs["Full Subtractor<br/>[FS.v]"]
  node_g_to_b["Gray to Binary<br/>[G_TO_B.v]"]
  node_ha["Half Adder<br/>[HA.v]"]
  node_hs["Half Subtractor<br/>[HS.v]"]
  node_mul2["2-bit Multiplier<br/>[MUL2.v]"]
  node_mul43["4-by-3 Multiplier<br/>[MUL43.v]"]
  node_four_bit_alu["4-bit ALU<br/>[FOUR_BIT_ALU.v]"]
  node_mux21["2-to-1 Mux<br/>[MUX_2_1.v]"]
  node_mux41["4-to-1 Mux<br/>[MUX_4_1.v]"]
  node_mux81["8-to-1 Mux<br/>[MUX_8_1.v]"]
  node_priority42["4-to-2 Priority Encoder"]
  node_priority83["8-to-3 Priority Encoder"]
end

subgraph group_seq["Sequential Logic"]
end

subgraph group_memory["Memory"]
end

subgraph group_interfaces["Interfaces"]
end

subgraph group_systems["Controllers and Systems"]
end

click node_add_sub "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/ADD_SUB.v"
click node_alu8 "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/ALU_8bit.v"
click node_aoi "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/AOI.v"
click node_basic_gates "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/BASIC_GATES.v"
click node_bcd_7seg "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/BCD_TO_7SEGMENT.v"
click node_bcd_decimal "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/BCD_TO_DECIMAL.v"
click node_b_to_e3 "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/B_TO_E3.v"
click node_b_to_g "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/B_TO_G.v"
click node_cla "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/CLA.v"
click node_comp1 "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/COMP1.v"
click node_comp2 "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/COMP2.v"
click node_comp4 "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/COMP_4.v"
click node_decoder24 "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/DECODER_2_4.v"
click node_decoder38 "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/DECODER_3_8.v"
click node_demux12 "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/DEMUX_1_2.v"
click node_demux14 "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/DEMUX_1_4.v"
click node_demux18 "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/DEMUX_1_8.v"
click node_e3_to_b "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/E3_TO_B.v"
click node_encoder42 "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/ENCODER4_2.v"
click node_encoder83 "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/ENCODER8_3.v"
click node_error_correction "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/ERROR_DETECTION_AND_CORRECTION.v"
click node_fa "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/FA.v"
click node_fs "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/FS.v"
click node_g_to_b "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/G_TO_B.v"
click node_ha "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/HA.v"
click node_hs "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/HS.v"
click node_mul2 "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/MUL2.v"
click node_mul43 "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/MUL43.v"
click node_four_bit_alu "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/FOUR_BIT_ALU.v"
click node_mux21 "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/MUX_2_1.v"
click node_mux41 "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/MUX_4_1.v"
click node_mux81 "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/MUX_8_1.v"
click node_priority42 "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/PRIORITY_ENCODER_4_2.v"
click node_priority83 "https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/PRIORITY_ENCODER_8_3.v"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_add_sub,node_alu8,node_aoi,node_basic_gates,node_bcd_7seg,node_bcd_decimal,node_b_to_e3,node_b_to_g,node_cla,node_comp1,node_comp2,node_comp4,node_decoder24,node_decoder38,node_demux12,node_demux14,node_demux18,node_e3_to_b,node_encoder42,node_encoder83,node_error_correction,node_fa,node_fs,node_g_to_b,node_ha,node_hs,node_mul2,node_mul43,node_four_bit_alu,node_mux21,node_mux41,node_mux81,node_priority42,node_priority83 toneBlue
```

## Components

### Combinational Logic

- [Add/Subtract](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/ADD_SUB.v): `ADD_SUB.v`
- [8-bit ALU](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/ALU_8bit.v): `ALU_8bit.v`
- [AOI Logic](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/AOI.v): `AOI.v`
- [Basic Gates](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/BASIC_GATES.v): `BASIC_GATES.v`
- [BCD to Seven-Segment](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/BCD_TO_7SEGMENT.v): `BCD_TO_7SEGMENT.v`
- [BCD to Decimal](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/BCD_TO_DECIMAL.v): `BCD_TO_DECIMAL.v`
- [Binary to Excess-3](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/B_TO_E3.v): `B_TO_E3.v`
- [Binary to Gray](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/B_TO_G.v): `B_TO_G.v`
- [Carry Lookahead Adder](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/CLA.v): `CLA.v`
- [Comparator 1](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/COMP1.v): `COMP1.v`
- [Comparator 2](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/COMP2.v): `COMP2.v`
- [4-bit Comparator](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/COMP_4.v): `COMP_4.v`
- [2-to-4 Decoder](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/DECODER_2_4.v): `DECODER_2_4.v`
- [3-to-8 Decoder](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/DECODER_3_8.v): `DECODER_3_8.v`
- [1-to-2 Demux](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/DEMUX_1_2.v): `DEMUX_1_2.v`
- [1-to-4 Demux](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/DEMUX_1_4.v): `DEMUX_1_4.v`
- [1-to-8 Demux](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/DEMUX_1_8.v): `DEMUX_1_8.v`
- [Excess-3 to Binary](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/E3_TO_B.v): `E3_TO_B.v`
- [4-to-2 Encoder](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/ENCODER4_2.v): `ENCODER4_2.v`
- [8-to-3 Encoder](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/ENCODER8_3.v): `ENCODER8_3.v`
- [Error Detection and Correction](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/ERROR_DETECTION_AND_CORRECTION.v): `ERROR_DETECTION_AND_CORRECTION.v`
- [Full Adder](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/FA.v): `FA.v`
- [Full Subtractor](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/FS.v): `FS.v`
- [Gray to Binary](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/G_TO_B.v): `G_TO_B.v`
- [Half Adder](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/HA.v): `HA.v`
- [Half Subtractor](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/HS.v): `HS.v`
- [2-bit Multiplier](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/MUL2.v): `MUL2.v`
- [4-by-3 Multiplier](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/MUL43.v): `MUL43.v`
- [4-bit ALU](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/FOUR_BIT_ALU.v): `FOUR_BIT_ALU.v`
- [2-to-1 Mux](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/MUX_2_1.v): `MUX_2_1.v`
- [4-to-1 Mux](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/MUX_4_1.v): `MUX_4_1.v`
- [8-to-1 Mux](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/MUX_8_1.v): `MUX_8_1.v`
- [4-to-2 Priority Encoder](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/PRIORITY_ENCODER_4_2.v): `PRIORITY_ENCODER_4_2.v`
- [8-to-3 Priority Encoder](https://github.com/deekshithag1320/100-day-verilog-challenge/blob/main/PRIORITY_ENCODER_8_3.v): `PRIORITY_ENCODER_8_3.v`