How code-with-akash45/vlsi-rtl-design-journey works
This repository is a set of standalone Verilog digital-logic exercises, not a single application workflow. The tree identifies combinational circuits, sequential state elements, and a traffic-light controller. With no README or source excerpts, module interfaces and inter-module calls cannot be verified, so the graph shows the documented-by-name circuit units without inferred wiring. Simulation outputs and testbenches are excluded.
Components 9
Combinational Logic
Sequential Logic
- D Flip-Flop
DAY5/dff.v - 4-bit Counter
DAY5/counter4.v
Control Logic
- Traffic-Light Controller
DAY6/traffic_light.v