# code-with-akash45/vlsi-rtl-design-journey architecture

> Architecture diagram of the GitHub repository code-with-akash45/vlsi-rtl-design-journey, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-28). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/code-with-akash45/vlsi-rtl-design-journey
- Repository: https://github.com/code-with-akash45/vlsi-rtl-design-journey

## Overview

This repository is a set of standalone Verilog digital-logic exercises, not a single application workflow. The tree identifies combinational circuits, sequential state elements, and a traffic-light controller. With no README or source excerpts, module interfaces and inter-module calls cannot be verified, so the graph shows the documented-by-name circuit units without inferred wiring. Simulation outputs and testbenches are excluded.

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_combinational["Combinational Logic"]
  node_and_gate["AND Gate<br/>[and_gate.v]"]
  node_mux2_day1["2:1 Mux<br/>[mux2x1.v]"]
  node_mux8["8:1 Mux<br/>[mux8x1.v]"]
  node_adder4["4-bit Adder<br/>[adder4.v]"]
  node_mux2_day3["2:1 Mux<br/>[mux2x1.v]"]
  node_alu4["4-bit ALU<br/>[alu4.v]"]
end

subgraph group_sequential["Sequential Logic"]
  node_dff["D Flip-Flop<br/>[dff.v]"]
  node_counter4["4-bit Counter<br/>[counter4.v]"]
end

subgraph group_control["Control Logic"]
  node_traffic_light["Traffic-Light Controller<br/>[traffic_light.v]"]
end

click node_and_gate "https://github.com/code-with-akash45/vlsi-rtl-design-journey/blob/main/DAY1/and_gate/and_gate.v"
click node_mux2_day1 "https://github.com/code-with-akash45/vlsi-rtl-design-journey/blob/main/DAY1/mux/mux2x1.v"
click node_mux8 "https://github.com/code-with-akash45/vlsi-rtl-design-journey/blob/main/DAY1/mux2/mux8x1.v"
click node_adder4 "https://github.com/code-with-akash45/vlsi-rtl-design-journey/blob/main/DAY2/adder4.v"
click node_mux2_day3 "https://github.com/code-with-akash45/vlsi-rtl-design-journey/blob/main/DAY3/mux2x1.v"
click node_alu4 "https://github.com/code-with-akash45/vlsi-rtl-design-journey/blob/main/DAY4/alu4.v"
click node_dff "https://github.com/code-with-akash45/vlsi-rtl-design-journey/blob/main/DAY5/dff.v"
click node_counter4 "https://github.com/code-with-akash45/vlsi-rtl-design-journey/blob/main/DAY5/counter4.v"
click node_traffic_light "https://github.com/code-with-akash45/vlsi-rtl-design-journey/blob/main/DAY6/traffic_light.v"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_and_gate,node_mux2_day1,node_mux8,node_adder4,node_mux2_day3,node_alu4 toneBlue
class node_dff,node_counter4 toneAmber
class node_traffic_light toneMint
```

## Components

### Combinational Logic

- [AND Gate](https://github.com/code-with-akash45/vlsi-rtl-design-journey/blob/main/DAY1/and_gate/and_gate.v): `DAY1/and_gate/and_gate.v`
- [2:1 Mux](https://github.com/code-with-akash45/vlsi-rtl-design-journey/blob/main/DAY1/mux/mux2x1.v): `DAY1/mux/mux2x1.v`
- [8:1 Mux](https://github.com/code-with-akash45/vlsi-rtl-design-journey/blob/main/DAY1/mux2/mux8x1.v): `DAY1/mux2/mux8x1.v`
- [4-bit Adder](https://github.com/code-with-akash45/vlsi-rtl-design-journey/blob/main/DAY2/adder4.v): `DAY2/adder4.v`
- [2:1 Mux](https://github.com/code-with-akash45/vlsi-rtl-design-journey/blob/main/DAY3/mux2x1.v): `DAY3/mux2x1.v`
- [4-bit ALU](https://github.com/code-with-akash45/vlsi-rtl-design-journey/blob/main/DAY4/alu4.v): `DAY4/alu4.v`

### Sequential Logic

- [D Flip-Flop](https://github.com/code-with-akash45/vlsi-rtl-design-journey/blob/main/DAY5/dff.v): `DAY5/dff.v`
- [4-bit Counter](https://github.com/code-with-akash45/vlsi-rtl-design-journey/blob/main/DAY5/counter4.v): `DAY5/counter4.v`

### Control Logic

- [Traffic-Light Controller](https://github.com/code-with-akash45/vlsi-rtl-design-journey/blob/main/DAY6/traffic_light.v): `DAY6/traffic_light.v`