abhishek1234563/4-bit-ripple-carry

How abhishek1234563/4-bit-ripple-carry works

The repository is an educational RTL-to-GDS flow for a 4-bit ripple-carry adder. The documented path runs simulation, synthesis, place-and-route, and physical verification before GDS export. The sampled driver confirms configuration loading and tool invocation; the RTL, testbench, and configuration contents were not sampled, so their internal wiring is shown only where the README documents it. The README mentions LVS, but the shown driver invokes Magic DRC only.

Main entry points: flow.py Flow driver · four_bit_adder.v 4-bit adder · tb_four_bit_adder.v Adder testbench · sky130_hd.yaml Sky130 config

Components 13

Flow orchestration

Flow driver flow.py
Sky130 config configs/sky130_hd.yaml

Adder design

4-bit adder src/four_bit_adder.v
Full adder src/full_adder.v

RTL implementation

Yosys synthesis
Synthesized netlist
OpenROAD place and route
Final GDSII

Verification and output

Adder testbench tb/tb_four_bit_adder.v
RTL simulation
Magic DRC
Netgen LVS

Other components

Flow user

Connections 13

Flow user → Flow driver: runs README.md
Flow driver → Sky130 config: loads flow.py
Flow driver → RTL simulation: runs flow.py
Adder testbench → RTL simulation: simulated by
4-bit adder → RTL simulation: simulated by
Flow driver → Yosys synthesis: invokes flow.py
4-bit adder → Yosys synthesis: synthesized by
Yosys synthesis → Synthesized netlist: writes
Flow driver → OpenROAD place and route: invokes flow.py
OpenROAD place and route → Final GDSII: exports README.md
Flow driver → Magic DRC: invokes flow.py
Flow driver → Netgen LVS: runs LVS
4-bit adder → Full adder: uses README.md

Drawn by GitDiagram on November 12, 2026 from the repository's file tree, README and source files. Read as Markdown ·