# abhishek1234563/4-bit-ripple-carry architecture

> Architecture diagram of the GitHub repository abhishek1234563/4-bit-ripple-carry, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-11-12). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/abhishek1234563/4-bit-ripple-carry
- Repository: https://github.com/abhishek1234563/4-bit-ripple-carry

## Overview

The repository is an educational RTL-to-GDS flow for a 4-bit ripple-carry adder. The documented path runs simulation, synthesis, place-and-route, and physical verification before GDS export. The sampled driver confirms configuration loading and tool invocation; the RTL, testbench, and configuration contents were not sampled, so their internal wiring is shown only where the README documents it. The README mentions LVS, but the shown driver invokes Magic DRC only.

Main entry points: [`flow.py`](https://github.com/abhishek1234563/4-bit-ripple-carry/blob/main/flow.py) (Flow driver), [`src/four_bit_adder.v`](https://github.com/abhishek1234563/4-bit-ripple-carry/blob/main/src/four_bit_adder.v) (4-bit adder), [`tb/tb_four_bit_adder.v`](https://github.com/abhishek1234563/4-bit-ripple-carry/blob/main/tb/tb_four_bit_adder.v) (Adder testbench), [`configs/sky130_hd.yaml`](https://github.com/abhishek1234563/4-bit-ripple-carry/blob/main/configs/sky130_hd.yaml) (Sky130 config)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_orchestration["Flow orchestration"]
  node_driver["Flow driver<br/>[flow.py]"]
  node_config["Sky130 config<br/>[sky130_hd.yaml]"]
end

subgraph group_design["Adder design"]
  node_adder["4-bit adder<br/>[four_bit_adder.v]"]
  node_full_adder["Full adder<br/>[full_adder.v]"]
end

subgraph group_implementation["RTL implementation"]
  node_yosys["Yosys synthesis"]
  node_netlist["Synthesized netlist"]
  node_openroad["OpenROAD place and route"]
  node_gds["Final GDSII"]
end

subgraph group_verification["Verification and output"]
  node_testbench["Adder testbench"]
  node_simulation["RTL simulation"]
  node_magic["Magic DRC"]
  node_netgen["Netgen LVS"]
end

node_user(("Flow user"))

node_user -->|"runs"| node_driver
node_driver -->|"loads"| node_config
node_driver -->|"runs"| node_simulation
node_testbench -->|"simulated by"| node_simulation
node_adder -->|"simulated by"| node_simulation
node_driver -->|"invokes"| node_yosys
node_adder -->|"synthesized by"| node_yosys
node_yosys -->|"writes"| node_netlist
node_driver -->|"invokes"| node_openroad
node_openroad -->|"exports"| node_gds
node_driver -->|"invokes"| node_magic
node_driver -.->|"runs LVS"| node_netgen
node_adder -.->|"uses"| node_full_adder

click node_driver "https://github.com/abhishek1234563/4-bit-ripple-carry/blob/main/flow.py"
click node_config "https://github.com/abhishek1234563/4-bit-ripple-carry/blob/main/configs/sky130_hd.yaml"
click node_adder "https://github.com/abhishek1234563/4-bit-ripple-carry/blob/main/src/four_bit_adder.v"
click node_full_adder "https://github.com/abhishek1234563/4-bit-ripple-carry/blob/main/src/full_adder.v"
click node_testbench "https://github.com/abhishek1234563/4-bit-ripple-carry/blob/main/tb/tb_four_bit_adder.v"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_driver,node_config,node_user toneBlue
class node_adder,node_full_adder toneAmber
class node_yosys,node_netlist,node_openroad,node_gds toneMint
class node_testbench,node_simulation,node_magic,node_netgen toneRose
```

## Components

### Flow orchestration

- [Flow driver](https://github.com/abhishek1234563/4-bit-ripple-carry/blob/main/flow.py): `flow.py`
- [Sky130 config](https://github.com/abhishek1234563/4-bit-ripple-carry/blob/main/configs/sky130_hd.yaml): `configs/sky130_hd.yaml`

### Adder design

- [4-bit adder](https://github.com/abhishek1234563/4-bit-ripple-carry/blob/main/src/four_bit_adder.v): `src/four_bit_adder.v`
- [Full adder](https://github.com/abhishek1234563/4-bit-ripple-carry/blob/main/src/full_adder.v): `src/full_adder.v`

### RTL implementation

- **Yosys synthesis**
- **Synthesized netlist**
- **OpenROAD place and route**
- **Final GDSII**

### Verification and output

- [Adder testbench](https://github.com/abhishek1234563/4-bit-ripple-carry/blob/main/tb/tb_four_bit_adder.v): `tb/tb_four_bit_adder.v`
- **RTL simulation**
- **Magic DRC**
- **Netgen LVS**

### Other components

- **Flow user**

## Connections

- Flow user → Flow driver: runs (evidence: `README.md`)
- Flow driver → Sky130 config: loads (evidence: `flow.py`)
- Flow driver → RTL simulation: runs (evidence: `flow.py`)
- Adder testbench → RTL simulation: simulated by
- 4-bit adder → RTL simulation: simulated by
- Flow driver → Yosys synthesis: invokes (evidence: `flow.py`)
- 4-bit adder → Yosys synthesis: synthesized by
- Yosys synthesis → Synthesized netlist: writes
- Flow driver → OpenROAD place and route: invokes (evidence: `flow.py`)
- OpenROAD place and route → Final GDSII: exports (evidence: `README.md`)
- Flow driver → Magic DRC: invokes (evidence: `flow.py`)
- Flow driver → Netgen LVS: runs LVS
- 4-bit adder → Full adder: uses (evidence: `README.md`)