weng20011103/zcu102_pynq

This repository is not one application; it is a ZCU102 PYNQ course kit. The architecture is a set of independent lesson projects that all use the same board/platform stack: ZCU102, Vivado 2020.2, and PYNQ v2.7.

The core system boundary is the classic Zynq split:

• Processing System (PS): ARM side running PYNQ/Python notebooks and scripts.

• Programmable Logic (PL): FPGA fabric containing RTL, AXI IP, clocking, DMA, and custom logic.

Most lessons demonstrate how the PS controls the PL through PYNQ abstractions such as GPIO, MMIO, and overlay loading. The notebooks are the user-facing control layer; the bitstreams, .hwh/.overlay metadata, and Vivado projects define the hardware layer.

The repo is organized by lesson, and each lesson is effectively a self-contained mini-architecture:

• Lesson 1–3: simplest GPIO-to-LED path, moving from direct GPIO use to XDC pin binding and then PYNQ bitstream loading.

• Lesson 4: PS-controlled GPIO driving an external DAC, showing board-level peripheral control.

• Lesson 5: clock generation and PS/bitstream constraints, including a frequency-divider RTL block and Clocking Wizard usage.

• Lesson 6: DMA-based data movement, focusing on streaming data between PS memory and PL logic.

• Lesson 7: HLS-generated IP integrated into a PYNQ workflow.

• Lesson 8: a custom AXI4-Lite IP block, showing register-mapped control logic.

• Lesson 9: Vivado TCL automation for reproducible hardware builds.

• Lesson 10: direct PYNQ MMIO access to registers, emphasizing low-level software control of PL hardware.

The dataflow patterns repeat across lessons and are important for a diagram:

• Notebook/script → PYNQ runtime on PS → AXI-Lite/MMIO/GPIO → PL registers or simple logic.

• Notebook/script → DMA buffers in memory → AXI DMA / AXI-Stream path → PL accelerator or FIFO.

• Vivado-generated hardware → bitstream + hardware handoff metadata → loaded by PYNQ as an overlay.

Hardware integration is expressed through constraints and pin mapping files:

• .xdc files bind FPGA signals to ZCU102 LEDs, DAC pins, PMOD headers, clocks, etc.

• RTL files (.v) define small blocks like LED logic, clock dividers, or AXI peripherals.

• HLS/IP artifacts and overlay descriptors connect higher-level generated IP to the same AXI infrastructure.

The supporting material is mostly instructional evidence rather than runtime code:

• Jupyter notebooks demonstrate PS-side control and testing.

• CSVs and plotting scripts capture scope measurements and validation data.

• Pictures and PDFs document expected waveforms, hardware behavior, and design notes.

• TCL scripts show automation for Vivado project creation or IP integration.

The main architectural diagram for this repo should therefore center on one ZCU102 board split into PS and PL, with multiple lesson-specific hardware blocks attached to the PL and multiple Python/Jupyter control paths on the PS. There is no single backend service or monolithic app; the repo is a catalog of hardware/software interaction patterns for FPGA development with PYNQ.