How valrek-sol/scanchain works
1. Repository purpose
- This repo is a small RTL/DFT experiment, not an application stack.
- The core goal is to show how a simple sequential design—a 4-bit synchronous counter—can be modified into a scan-enabled design for testability.
2. Main design boundary: functional RTL vs scan RTL
- src/four_bit_counter.v is the plain functional counter implementation.
- src/four_bit_counter_scan.v is the scan-inserted version, where flip-flops are effectively wrapped with scan capability.
- The architectural shift is from normal state storage to a design that supports both normal operation and test-mode shifting.
3. Scan chain structure
- The scan version uses a chain of scan DFF behavior: each register bit can load either normal functional data or a scan input through a 2:1 mux.
- The register outputs are chained so that one flip-flop’s Q feeds the next flip-flop’s scan input, enabling serial shift-in and shift-out of internal state.
- This makes the internal counter state observable and controllable from the outside.
4. Operational modes
- The design has two meaningful modes:
- Functional mode: the counter behaves as a synchronous 4-bit counter.
- Scan/test mode: internal state is shifted through the scan chain using test_si and test_so-style connectivity.
- The README describes a capture/shift example using a scan-in pattern of 1010 and checking the resulting shifted-out state.
5. Verification subsystem
- src/four_bit_counter_scan_tb.v is the testbench used to stimulate the scan design.
- It exercises the scan interface and produces simulation output for waveform inspection.
- src/scan_sim.vcd is the waveform dump generated by simulation and viewed in GTKWave.
6. Synthesis flow
- synth.ys is the Yosys synthesis script that drives the flow.
- It reads four_bit_counter_scan.v, synthesizes four_bit_counter_scan as the top module, and emits both:
- src/synth_netlist.v for gate-level/post-synthesis simulation
- src/counter_scan.blif for logic-network export
- src/synth_stats.txt captures synthesis statistics, which is useful for understanding how the scan logic affects cell count and structure.
7. Post-synthesis simulation boundary
- The repo explicitly separates RTL-level scan behavior from synthesized netlist behavior.
- src/post_synth_sim is the executable produced by Icarus Verilog using the synthesized netlist plus the testbench.
- This gives a check that the scan behavior still works after synthesis, not just at the RTL level.
8. Toolchain dependency
- The architecture depends on a standard open-source EDA flow:
- Yosys for synthesis and netlist generation
- Icarus Verilog for simulation
- GTKWave for waveform debug
- These tools are not part of the design itself, but they define the repo’s build/analysis pipeline.
9. Generated vs source artifacts
- Source files are the hand-authored RTL, testbench, and synthesis script.
- Generated artifacts are the netlist, BLIF, statistics, waveform, and simulation executable.
- For an architecture diagram, it helps to draw a clear boundary between authored design inputs and tool-generated outputs.
10. Overall data flow
- RTL scan design → Yosys synthesis → synthesized netlist/BLIF/stats → Icarus simulation with testbench → VCD waveform → GTKWave inspection.
- The key architectural idea is that the scan chain provides a controllable path into and out of sequential state, enabling deterministic test access to the counter’s internal registers.
11. What this repo is demonstrating
- This is a pedagogical DFT example rather than a production scan insertion flow.
- The emphasis is on understanding the mechanics of scan chains in a small sequential circuit and validating them through synthesis and simulation.
Main entry points: four_bit_counter_scan.v Scan counter · README.md README · four_bit_counter_scan_tb.v Testbench · post_synth_sim Post-synth sim
Components 14
Authored RTL
Hand-written design, testbench, and flow script.
- README · Explains the scan-chain example and workflow.
README.md - Counter · Plain 4-bit synchronous counter.
src/four_bit_counter.v - Scan counter · 4-bit counter with scan-inserted state storage.
src/four_bit_counter_scan.v - Testbench · Stimulus for scan and post-synthesis simulation.
src/four_bit_counter_scan_tb.v - Synthesis script · Yosys script that drives synthesis of the scan design.
synth.ys
Tool Flow
Synthesis and simulation tools that transform the design.
- Yosys · Synthesizes RTL into netlist and BLIF outputs.
- Icarus Verilog · Runs RTL and gate-level simulation.
- GTKWave · Inspects dumped simulation waveforms.
Generated Artifacts
Outputs produced by synthesis and simulation.
- Netlist · Synthesized Verilog netlist for gate-level simulation.
src/synth_netlist.v - BLIF · Logic-network export from synthesis.
src/counter_scan.blif - Stats · Synthesis statistics for the scan design.
src/synth_stats.txt - Post-synth sim · Executable that simulates the synthesized netlist with the testbench.
src/post_synth_sim - VCD · Simulation waveform dump for debug.
src/scan_sim.vcd - Synthesis diagram · Graphviz view of the synthesized structure.
src/synth_diagram.dot
Connections 18
- README → Counter: describes · Documents the functional counter baseline.
- README → Scan counter: explains · Documents the scan-enabled variant and test mode.
- README → Testbench: shows · Describes the scan testbench and capture/shift example.
- README → Synthesis script: outlines · Explains the synthesis flow and emitted artifacts.
- Counter → Scan counter: baseline · Functional RTL is the starting point for scan insertion.
- Scan counter → Testbench: verified by · The testbench exercises scan-in and scan-out behavior.
- Scan counter → Synthesis script: input · The scan RTL is the synthesis target.
- Synthesis script → Yosys: drives · Yosys executes the synthesis flow.
- Yosys → Netlist: emits · Produces the synthesized Verilog netlist.
- Yosys → BLIF: emits · Produces a BLIF logic-network export.
- Yosys → Stats: reports · Produces synthesis statistics.
- Netlist → Post-synth sim: linked into · The synthesized netlist is used for gate-level simulation.
- Testbench → Post-synth sim: drives · The testbench stimulates the post-synthesis executable.
- Post-synth sim → VCD: dumps · Simulation generates a waveform trace.
- VCD → GTKWave: viewed in · Waveform output is inspected in GTKWave.
- Testbench → Icarus Verilog: run by · Icarus Verilog compiles and runs the simulation.
- Icarus Verilog → Post-synth sim: builds · Produces the post-synthesis simulation executable.
- Scan counter → Synthesis diagram: visualized by · A structural diagram of the synthesized scan logic.