# tuannamnguyen1902/edabk_verilog architecture

> Architecture diagram of the GitHub repository tuannamnguyen1902/edabk_verilog, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-11-12). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/tuannamnguyen1902/edabk_verilog
- Repository: https://github.com/tuannamnguyen1902/edabk_verilog

## Overview

This repository is a collection of independent hardware and arithmetic exercises rather than one integrated product. The only sampled implementation is a C++ reference program for an 8×8 matrix-vector multiply: it computes each row’s dot product, stores the eight outputs, and prints them. The tree also contains separate UART, clock, ALU, FIR, MAC, and matrix-vector HDL projects, but there is no README and their source was not sampled, so their internal wiring is not established here.

Main entry points: [`RISC_V/matrix_mul.cpp`](https://github.com/tuannamnguyen1902/edabk_verilog/blob/main/RISC_V/matrix_mul.cpp) (Matrix multiply)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_software["Software reference"]
  node_matmul["Matrix multiply<br/>[matrix_mul.cpp]"]
  node_riscv_asm["RISC-V assembly<br/>[matrix_mul.s]"]
end

subgraph group_hdl["HDL projects"]
  node_uart["APB UART"]
  node_alu["4-bit ALU"]
  node_clock["Century clock"]
  node_fir["8-tap FIR"]
  node_mac["MAC variants"]
  node_matvec["Matrix-vector HDL<br/>[matvec_mult.v]"]
  node_bailab["16-bit adder"]
end

node_developer(("Program user"))

node_developer -->|"runs"| node_matmul
node_matmul -->|"prints results"| node_developer

click node_matmul "https://github.com/tuannamnguyen1902/edabk_verilog/blob/main/RISC_V/matrix_mul.cpp"
click node_uart "https://github.com/tuannamnguyen1902/edabk_verilog/tree/main/UART/hdl"
click node_alu "https://github.com/tuannamnguyen1902/edabk_verilog/tree/main/alu4bit"
click node_clock "https://github.com/tuannamnguyen1902/edabk_verilog/tree/main/century_clock"
click node_fir "https://github.com/tuannamnguyen1902/edabk_verilog/tree/main/fir_8tap"
click node_mac "https://github.com/tuannamnguyen1902/edabk_verilog/tree/main/m_ac"
click node_matvec "https://github.com/tuannamnguyen1902/edabk_verilog/tree/main/matvec_mult.v"
click node_riscv_asm "https://github.com/tuannamnguyen1902/edabk_verilog/blob/main/RISC_V/matrix_mul.s"
click node_bailab "https://github.com/tuannamnguyen1902/edabk_verilog/tree/main/bailab3"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_matmul,node_riscv_asm,node_developer toneBlue
class node_uart,node_alu,node_clock,node_fir,node_mac,node_matvec,node_bailab toneAmber
```

## Components

### Software reference

- [Matrix multiply](https://github.com/tuannamnguyen1902/edabk_verilog/blob/main/RISC_V/matrix_mul.cpp): `RISC_V/matrix_mul.cpp`
- [RISC-V assembly](https://github.com/tuannamnguyen1902/edabk_verilog/blob/main/RISC_V/matrix_mul.s): `RISC_V/matrix_mul.s`

### HDL projects

- [APB UART](https://github.com/tuannamnguyen1902/edabk_verilog/tree/main/UART/hdl): `UART/hdl`
- [4-bit ALU](https://github.com/tuannamnguyen1902/edabk_verilog/tree/main/alu4bit): `alu4bit`
- [Century clock](https://github.com/tuannamnguyen1902/edabk_verilog/tree/main/century_clock): `century_clock`
- [8-tap FIR](https://github.com/tuannamnguyen1902/edabk_verilog/tree/main/fir_8tap): `fir_8tap`
- [MAC variants](https://github.com/tuannamnguyen1902/edabk_verilog/tree/main/m_ac): `m_ac`
- [Matrix-vector HDL](https://github.com/tuannamnguyen1902/edabk_verilog/tree/main/matvec_mult.v): `matvec_mult.v`
- [16-bit adder](https://github.com/tuannamnguyen1902/edabk_verilog/tree/main/bailab3): `bailab3`

### Other components

- **Program user**

## Connections

- Program user → Matrix multiply: runs (evidence: `RISC_V/matrix_mul.cpp`)
- Matrix multiply → Program user: prints results (evidence: `RISC_V/matrix_mul.cpp`)