How thp-tran/uart_vip works
This is a SystemVerilog/UVM UART verification IP: engineers run tests that exercise UART configurations and error scenarios against a DUT. The README documents the VIP component roles and the test/sequence coverage, but no source excerpts were available to confirm internal calls or exact wiring; links therefore show only documented verification relationships, not a detailed runtime pipeline.
Main entry points: testcases Test cases · sequences Sequence suite · uart_driver.sv Driver · uart_dut.sv UART DUT
Components 16
Tests and scenarios
- Test cases
testcases - Base test
testcases/uart_vip_base_test.sv
Traffic generation
- Sequence suite
sequences - Error and recovery
sequences/uart_error_sequence.sv - Pattern and traffic
sequences/uart_pattern_sequence.sv
UART VIP
- UART agent
vip/uart_agent.sv - Sequencer
vip/uart_sequencer.sv - Driver
vip/uart_driver.sv - Monitor
vip/uart_monitor.sv - Transaction
vip/uart_transaction.sv - Configuration
vip/uart_configuration.sv - UART interface
vip/uart_if.sv
Verification bench
- Test environment
tb/uart_env.sv - Scoreboard
tb/uart_scoreboard.sv - UART DUT
rtl/uart_dut.sv
Other components
- Verification engineer
Connections 3
- Verification engineer → Test cases: selects
- Test cases → UART DUT: verify configurations
- Sequence suite → Driver: generates traffic for