# the-silis-foundation/silis architecture

> Architecture diagram of the GitHub repository the-silis-foundation/silis, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-11-09). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/the-silis-foundation/silis
- Repository: https://github.com/the-silis-foundation/silis

## Overview

Silis is an end-to-end RTL-to-GDSII ASIC design studio with GUI, CLI, and Python SDK interfaces. The principal workflow takes RTL and constraints through synthesis and formal checks, physical planning and power intent, then toward layout and signoff; the README also describes DFT, simulation, and interactive design inspection. The graph preserves these major capabilities, while relationships beyond the README’s pipeline excerpt are omitted or marked unverified because their callers were not sampled.

Main entry points: [`core/sdk/pipeline.py`](https://github.com/the-silis-foundation/silis/blob/main/core/sdk/pipeline.py) (Flow Pipeline), [`core/backendflow/floorplanner/floorplanner.py`](https://github.com/the-silis-foundation/silis/blob/main/core/backendflow/floorplanner/floorplanner.py) (Floorplanning), [`core/cli/main.py`](https://github.com/the-silis-foundation/silis/blob/main/core/cli/main.py) (CLI Tools), [`core/backendflow/gds_snapshot.py`](https://github.com/the-silis-foundation/silis/blob/main/core/backendflow/gds_snapshot.py) (Layout Snapshot)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_entry["Project Entry"]
  node_cli["CLI Tools<br/>[main.py]"]
  node_project[("Project Registry")]
  node_intake["RTL Intake"]
end

subgraph group_implementation["Design Implementation"]
  node_pipeline["Flow Pipeline<br/>[pipeline.py]"]
  node_synthesis["Synthesis<br/>[synthesisthread.py]"]
  node_floorplan["Floorplanning<br/>[floorplanner.py]"]
  node_regions["Region Placement"]
  node_powerintent["Power Intent<br/>[upf_engine.py]"]
  node_layout["Layout Snapshot<br/>[gds_snapshot.py]"]
  node_tapeout["Tapeout Fill<br/>[fill_engine.py]"]
end

subgraph group_verification["Verification"]
  node_dft["DFT Scan<br/>[dft_engine.py]"]
  node_gls["Gate Simulation<br/>[gls_engine.py]"]
  node_lvs["LVS Signoff<br/>[lvs_engine.py]"]
  node_reports["Signoff Reports<br/>[signoff_report.py]"]
end

subgraph group_inspection["Design Inspection"]
  node_peeker["Layout Viewer<br/>[peeker.py]"]
  node_schematic["Schematic Viewer"]
  node_waveforms["Waveform Viewer"]
end

subgraph group_platform["SDK and Platform"]
  node_pdks["PDK Manager<br/>[manager.py]"]
  node_sdk["Python SDK"]
end

node_engineer(("ASIC Engineer"))

node_engineer -->|"starts flow"| node_cli
node_engineer -->|"automates design"| node_sdk
node_cli -->|"manages projects"| node_project
node_cli -->|"runs flow"| node_pipeline
node_intake -.->|"provides RTL"| node_synthesis
node_pipeline -.->|"orchestrates"| node_synthesis
node_pipeline -->|"invokes planning"| node_floorplan
node_floorplan -->|"uses placement"| node_regions
node_floorplan -->|"reads intent"| node_powerintent
node_floorplan -->|"queries PDK"| node_pdks
node_pipeline -->|"invokes placement"| node_regions
node_pipeline -->|"uses snapshots"| node_layout
node_layout -->|"supports fill"| node_tapeout
node_engineer -->|"configures scan"| node_dft
node_engineer -->|"runs simulation"| node_gls
node_engineer -->|"checks layout"| node_lvs
node_engineer -->|"inspects layout"| node_peeker
node_engineer -->|"inspects logic"| node_schematic
node_engineer -->|"views traces"| node_waveforms
node_pipeline -.->|"supports signoff"| node_reports

click node_cli "https://github.com/the-silis-foundation/silis/blob/main/core/cli/main.py"
click node_project "https://github.com/the-silis-foundation/silis/blob/main/core/project_registry.py"
click node_intake "https://github.com/the-silis-foundation/silis/tree/main/core/intake"
click node_pipeline "https://github.com/the-silis-foundation/silis/blob/main/core/sdk/pipeline.py"
click node_synthesis "https://github.com/the-silis-foundation/silis/blob/main/core/synthesisscripts/synthesisthread.py"
click node_floorplan "https://github.com/the-silis-foundation/silis/blob/main/core/backendflow/floorplanner/floorplanner.py"
click node_regions "https://github.com/the-silis-foundation/silis/blob/main/core/backendflow/floorplanner/region_autoplacer.py"
click node_powerintent "https://github.com/the-silis-foundation/silis/blob/main/core/backendflow/power/upf_engine.py"
click node_pdks "https://github.com/the-silis-foundation/silis/blob/main/core/pdkmanagers/pdk/manager.py"
click node_layout "https://github.com/the-silis-foundation/silis/blob/main/core/backendflow/gds_snapshot.py"
click node_tapeout "https://github.com/the-silis-foundation/silis/blob/main/core/tapeout/fill_engine.py"
click node_dft "https://github.com/the-silis-foundation/silis/blob/main/core/dft/dft_engine.py"
click node_gls "https://github.com/the-silis-foundation/silis/blob/main/core/simulation/gls_engine.py"
click node_lvs "https://github.com/the-silis-foundation/silis/blob/main/core/lvs/lvs_engine.py"
click node_reports "https://github.com/the-silis-foundation/silis/blob/main/core/backendflow/signoff_report.py"
click node_peeker "https://github.com/the-silis-foundation/silis/blob/main/core/backendflow/siliconpeeker/peeker.py"
click node_schematic "https://github.com/the-silis-foundation/silis/tree/main/core/schematicviewer"
click node_waveforms "https://github.com/the-silis-foundation/silis/tree/main/core/signalpeeker"
click node_sdk "https://github.com/the-silis-foundation/silis/tree/main/core/sdk"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_cli,node_project,node_intake toneBlue
class node_pipeline,node_synthesis,node_floorplan,node_regions,node_powerintent,node_layout,node_tapeout toneAmber
class node_dft,node_gls,node_lvs,node_reports toneMint
class node_peeker,node_schematic,node_waveforms toneRose
class node_pdks,node_sdk,node_engineer toneIndigo
```

## Components

### Project Entry

- [CLI Tools](https://github.com/the-silis-foundation/silis/blob/main/core/cli/main.py): `core/cli/main.py`
- [Project Registry](https://github.com/the-silis-foundation/silis/blob/main/core/project_registry.py): `core/project_registry.py`
- [RTL Intake](https://github.com/the-silis-foundation/silis/tree/main/core/intake): `core/intake`

### Design Implementation

- [Flow Pipeline](https://github.com/the-silis-foundation/silis/blob/main/core/sdk/pipeline.py): `core/sdk/pipeline.py`
- [Synthesis](https://github.com/the-silis-foundation/silis/blob/main/core/synthesisscripts/synthesisthread.py): `core/synthesisscripts/synthesisthread.py`
- [Floorplanning](https://github.com/the-silis-foundation/silis/blob/main/core/backendflow/floorplanner/floorplanner.py): `core/backendflow/floorplanner/floorplanner.py`
- [Region Placement](https://github.com/the-silis-foundation/silis/blob/main/core/backendflow/floorplanner/region_autoplacer.py): `core/backendflow/floorplanner/region_autoplacer.py`
- [Power Intent](https://github.com/the-silis-foundation/silis/blob/main/core/backendflow/power/upf_engine.py): `core/backendflow/power/upf_engine.py`
- [Layout Snapshot](https://github.com/the-silis-foundation/silis/blob/main/core/backendflow/gds_snapshot.py): `core/backendflow/gds_snapshot.py`
- [Tapeout Fill](https://github.com/the-silis-foundation/silis/blob/main/core/tapeout/fill_engine.py): `core/tapeout/fill_engine.py`

### Verification

- [DFT Scan](https://github.com/the-silis-foundation/silis/blob/main/core/dft/dft_engine.py): `core/dft/dft_engine.py`
- [Gate Simulation](https://github.com/the-silis-foundation/silis/blob/main/core/simulation/gls_engine.py): `core/simulation/gls_engine.py`
- [LVS Signoff](https://github.com/the-silis-foundation/silis/blob/main/core/lvs/lvs_engine.py): `core/lvs/lvs_engine.py`
- [Signoff Reports](https://github.com/the-silis-foundation/silis/blob/main/core/backendflow/signoff_report.py): `core/backendflow/signoff_report.py`

### Design Inspection

- [Layout Viewer](https://github.com/the-silis-foundation/silis/blob/main/core/backendflow/siliconpeeker/peeker.py): `core/backendflow/siliconpeeker/peeker.py`
- [Schematic Viewer](https://github.com/the-silis-foundation/silis/tree/main/core/schematicviewer): `core/schematicviewer`
- [Waveform Viewer](https://github.com/the-silis-foundation/silis/tree/main/core/signalpeeker): `core/signalpeeker`

### SDK and Platform

- [PDK Manager](https://github.com/the-silis-foundation/silis/blob/main/core/pdkmanagers/pdk/manager.py): `core/pdkmanagers/pdk/manager.py`
- [Python SDK](https://github.com/the-silis-foundation/silis/tree/main/core/sdk): `core/sdk`

### Other components

- **ASIC Engineer**

## Connections

- ASIC Engineer → CLI Tools: starts flow
- ASIC Engineer → Python SDK: automates design
- CLI Tools → Project Registry: manages projects (evidence: `core/cli/main.py`)
- CLI Tools → Flow Pipeline: runs flow
- RTL Intake → Synthesis: provides RTL
- Flow Pipeline → Synthesis: orchestrates
- Flow Pipeline → Floorplanning: invokes planning (evidence: `core/sdk/pipeline.py`)
- Floorplanning → Region Placement: uses placement (evidence: `core/backendflow/floorplanner/floorplanner.py`)
- Floorplanning → Power Intent: reads intent (evidence: `core/backendflow/floorplanner/floorplanner.py`)
- Floorplanning → PDK Manager: queries PDK (evidence: `core/backendflow/floorplanner/floorplanner.py`)
- Flow Pipeline → Region Placement: invokes placement (evidence: `core/sdk/pipeline.py`)
- Flow Pipeline → Layout Snapshot: uses snapshots (evidence: `core/sdk/pipeline.py`)
- Layout Snapshot → Tapeout Fill: supports fill (evidence: `core/tapeout/fill_engine.py`)
- ASIC Engineer → DFT Scan: configures scan
- ASIC Engineer → Gate Simulation: runs simulation
- ASIC Engineer → LVS Signoff: checks layout
- ASIC Engineer → Layout Viewer: inspects layout
- ASIC Engineer → Schematic Viewer: inspects logic
- ASIC Engineer → Waveform Viewer: views traces
- Flow Pipeline → Signoff Reports: supports signoff