# sstsimulator/sst-elements architecture

> Architecture diagram of the GitHub repository sstsimulator/sst-elements, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-30). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/sstsimulator/sst-elements
- Repository: https://github.com/sstsimulator/sst-elements

## Overview

SST Elements is a modular, MPI-parallel simulation framework for studying interactions among processors, memory, and communication systems. A typical workflow configures a workload and system components, then advances simulated events across component links to model behavior and produce measurements. The graph highlights workload generation, memory and network modeling, and fault injection. Evidence is limited to the README, file tree, and sampled excerpts: several subsystems are represented by their documented or indexed modules, but their internal runtime wiring is not asserted where it was not shown.

Main entry points: [`src/sst/elements/ember/emberengine.cc`](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/ember/emberengine.cc) (Ember Engine), [`src/sst/elements/ember/embergen.h`](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/ember/embergen.h) (Motif Generator), [`src/sst/elements/memHierarchy/memEvent.h`](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/memEvent.h) (Memory Events), [`src/sst/elements/memHierarchy`](https://github.com/sstsimulator/sst-elements/tree/master/src/sst/elements/memHierarchy) (Memory Hierarchy)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_workloads["Workload Modeling"]
  node_ember["Ember Engine<br/>[emberengine.cc]"]
  node_motifs["Workload Motifs"]
  node_embergen["Motif Generator<br/>[embergen.h]"]
end

subgraph group_memory["Memory Systems"]
  node_memhier["Memory Hierarchy"]
  node_coherence["Coherence Controller"]
  node_directory["Directory Controller"]
  node_mem_events["Memory Events<br/>[memEvent.h]"]
  node_mem_nic["Memory NIC<br/>[memNIC.h]"]
  node_sieve["Sieve Cache<br/>[sieveController.cc]"]
  node_mem_dma["Memory DMA<br/>[dmaEngine.cc]"]
  node_cramsim["DRAM Controller<br/>[c_Controller.cc]"]
  node_cram_device["DRAM Device<br/>[c_DeviceDriver.hpp]"]
end

subgraph group_network["Network Modeling"]
  node_merlin["Network Router<br/>[hr_router.cc]"]
  node_rdma["RDMA NIC<br/>[rdmaNic.h]"]
  node_rdma_recv["RDMA Receive"]
  node_rdma_send["RDMA Send"]
end

subgraph group_extensions["Simulation Extensions"]
  node_ariel["Application CPU<br/>[arielcpu.cc]"]
  node_balar_dma["Balar DMA<br/>[dmaEngine.cc]"]
  node_fault_manager["Fault Manager<br/>[faultInjManager.cc]"]
  node_fault_models["Fault Models"]
end

node_user(("Modeler"))
node_measurements["Simulation Results"]

node_user -.->|"configures"| node_ember
node_user -.->|"configures"| node_memhier
node_ember -->|"initializes"| node_embergen
node_ember -->|"generates events"| node_embergen
node_motifs -.->|"implements"| node_embergen
node_embergen -.->|"drives simulation"| node_measurements
node_coherence -->|"handles"| node_mem_events
node_directory -->|"uses"| node_mem_nic
node_memhier -.->|"exchanges"| node_mem_events
node_mem_nic -->|"routes"| node_mem_events
node_sieve -->|"filters"| node_mem_events
node_mem_dma -->|"sends packets"| node_mem_nic
node_cramsim -->|"sends commands"| node_cram_device
node_cram_device -.->|"returns responses"| node_cramsim
node_rdma -->|"dispatches packets"| node_rdma_recv
node_rdma_recv -->|"queues read response"| node_rdma_send
node_rdma_send -.->|"serves send engine"| node_rdma
node_merlin -.->|"connects network"| node_rdma
node_ariel -.->|"models memory access"| node_memhier
node_balar_dma -.->|"models transfers"| node_measurements
node_fault_manager -.->|"manages"| node_fault_models
node_fault_manager -.->|"supports fault studies"| node_measurements
node_ember -.->|"produces simulation events"| node_measurements

click node_ember "https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/ember/emberengine.cc"
click node_motifs "https://github.com/sstsimulator/sst-elements/tree/master/src/sst/elements/ember/mpi/motifs"
click node_embergen "https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/ember/embergen.h"
click node_memhier "https://github.com/sstsimulator/sst-elements/tree/master/src/sst/elements/memHierarchy"
click node_coherence "https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/coherencemgr/coherenceController.cc"
click node_directory "https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/directoryController.cc"
click node_mem_events "https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/memEvent.h"
click node_mem_nic "https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/memNIC.h"
click node_sieve "https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/Sieve/sieveController.cc"
click node_mem_dma "https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/dmaEngine.cc"
click node_cramsim "https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/cramSim/c_Controller.cc"
click node_cram_device "https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/cramSim/c_DeviceDriver.hpp"
click node_merlin "https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/merlin/hr_router/hr_router.cc"
click node_rdma "https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/rdmaNic/rdmaNic.h"
click node_rdma_recv "https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/rdmaNic/rdmaNicRecvEngine.cc"
click node_rdma_send "https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/rdmaNic/rdmaNicSendEngine.cc"
click node_ariel "https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/ariel/arielcpu.cc"
click node_balar_dma "https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/dmaEngine.cc"
click node_fault_manager "https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/carcosa/components/faultInjManager.cc"
click node_fault_models "https://github.com/sstsimulator/sst-elements/tree/master/src/sst/elements/carcosa/faultlogic"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_ember,node_motifs,node_embergen toneBlue
class node_memhier,node_coherence,node_directory,node_mem_events,node_mem_nic,node_sieve,node_mem_dma,node_cramsim,node_cram_device toneAmber
class node_merlin,node_rdma,node_rdma_recv,node_rdma_send toneMint
class node_ariel,node_balar_dma,node_fault_manager,node_fault_models toneRose
class node_user,node_measurements toneIndigo
```

## Components

### Workload Modeling

- [Ember Engine](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/ember/emberengine.cc): `src/sst/elements/ember/emberengine.cc`
- [Workload Motifs](https://github.com/sstsimulator/sst-elements/tree/master/src/sst/elements/ember/mpi/motifs): `src/sst/elements/ember/mpi/motifs`
- [Motif Generator](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/ember/embergen.h): `src/sst/elements/ember/embergen.h`

### Memory Systems

- [Memory Hierarchy](https://github.com/sstsimulator/sst-elements/tree/master/src/sst/elements/memHierarchy): `src/sst/elements/memHierarchy`
- [Coherence Controller](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/coherencemgr/coherenceController.cc): `src/sst/elements/memHierarchy/coherencemgr/coherenceController.cc`
- [Directory Controller](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/directoryController.cc): `src/sst/elements/memHierarchy/directoryController.cc`
- [Memory Events](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/memEvent.h): `src/sst/elements/memHierarchy/memEvent.h`
- [Memory NIC](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/memNIC.h): `src/sst/elements/memHierarchy/memNIC.h`
- [Sieve Cache](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/Sieve/sieveController.cc): `src/sst/elements/memHierarchy/Sieve/sieveController.cc`
- [Memory DMA](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/memHierarchy/dmaEngine.cc): `src/sst/elements/memHierarchy/dmaEngine.cc`
- [DRAM Controller](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/cramSim/c_Controller.cc): `src/sst/elements/cramSim/c_Controller.cc`
- [DRAM Device](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/cramSim/c_DeviceDriver.hpp): `src/sst/elements/cramSim/c_DeviceDriver.hpp`

### Network Modeling

- [Network Router](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/merlin/hr_router/hr_router.cc): `src/sst/elements/merlin/hr_router/hr_router.cc`
- [RDMA NIC](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/rdmaNic/rdmaNic.h): `src/sst/elements/rdmaNic/rdmaNic.h`
- [RDMA Receive](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/rdmaNic/rdmaNicRecvEngine.cc): `src/sst/elements/rdmaNic/rdmaNicRecvEngine.cc`
- [RDMA Send](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/rdmaNic/rdmaNicSendEngine.cc): `src/sst/elements/rdmaNic/rdmaNicSendEngine.cc`

### Simulation Extensions

- [Application CPU](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/ariel/arielcpu.cc): `src/sst/elements/ariel/arielcpu.cc`
- [Balar DMA](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/balar/dmaEngine.cc): `src/sst/elements/balar/dmaEngine.cc`
- [Fault Manager](https://github.com/sstsimulator/sst-elements/blob/master/src/sst/elements/carcosa/components/faultInjManager.cc): `src/sst/elements/carcosa/components/faultInjManager.cc`
- [Fault Models](https://github.com/sstsimulator/sst-elements/tree/master/src/sst/elements/carcosa/faultlogic): `src/sst/elements/carcosa/faultlogic`

### Other components

- **Modeler**
- **Simulation Results**

## Connections

- Modeler → Ember Engine: configures
- Modeler → Memory Hierarchy: configures
- Ember Engine → Motif Generator: initializes (evidence: `src/sst/elements/ember/emberengine.cc`)
- Ember Engine → Motif Generator: generates events (evidence: `src/sst/elements/ember/emberengine.cc`)
- Workload Motifs → Motif Generator: implements
- Motif Generator → Simulation Results: drives simulation
- Coherence Controller → Memory Events: handles
- Directory Controller → Memory NIC: uses (evidence: `src/sst/elements/memHierarchy/directoryController.cc`)
- Memory Hierarchy → Memory Events: exchanges (evidence: `src/sst/elements/memHierarchy/dmaEngine.h`)
- Memory NIC → Memory Events: routes (evidence: `src/sst/elements/memHierarchy/memNIC.h`)
- Sieve Cache → Memory Events: filters (evidence: `src/sst/elements/memHierarchy/Sieve/sieveController.cc`)
- Memory DMA → Memory NIC: sends packets
- DRAM Controller → DRAM Device: sends commands (evidence: `src/sst/elements/cramSim/c_Controller.cc`)
- DRAM Device → DRAM Controller: returns responses (evidence: `src/sst/elements/cramSim/c_Controller.cc`)
- RDMA NIC → RDMA Receive: dispatches packets (evidence: `src/sst/elements/rdmaNic/rdmaNicRecvEngine.cc`)
- RDMA Receive → RDMA Send: queues read response (evidence: `src/sst/elements/rdmaNic/rdmaNicRecvEngine.cc`)
- RDMA Send → RDMA NIC: serves send engine (evidence: `src/sst/elements/rdmaNic/rdmaNicSendEngine.cc`)
- Network Router → RDMA NIC: connects network
- Application CPU → Memory Hierarchy: models memory access
- Balar DMA → Simulation Results: models transfers
- Fault Manager → Fault Models: manages (evidence: `src/sst/elements/carcosa/components/faultInjManager.cc`)
- Fault Manager → Simulation Results: supports fault studies
- Ember Engine → Simulation Results: produces simulation events