How souvlakiboi/ov7670_camera works
This is an FPGA camera-to-display design: it configures an OV7670 camera, captures its video into frame memory, and reads pixels for display output through an HDMI converter. The README documents the major stages and required Vivado IP, but no HDL excerpts were available, so internal module wiring and some control relationships are not asserted.
Main entry points: cam_capture.v Pixel capture · vga_top.v Display subsystem · RD_hdmi_ip2020.zip VGA-to-HDMI IP · top.v Top-level design
Components 16
System integration
- Top-level design
sources/hdl/top.v - Clock generator
Camera control
- Camera subsystem
sources/hdl/cam_top.v - Camera initializer
sources/hdl/cam_init.v - Camera configuration
sources/hdl/cam_config.v - Register settings
sources/hdl/cam_rom.v - SCCB controller
sources/hdl/sccb_master.v
Video capture
- Pixel capture
sources/hdl/cam_capture.v - Frame memory
- Debounce logic
sources/hdl/debounce.v
Display output
- Display subsystem
sources/hdl/vga_top.v - VGA timing driver
sources/hdl/vga_driver.v - VGA-to-HDMI IP
IP/RD_hdmi_ip2020.zip
Other components
- Urbana FPGA
- OV7670 camera
- HDMI monitor
Connections 6
- OV7670 camera → Pixel capture: sends video
- Pixel capture → Frame memory: writes pixels
- Frame memory → Display subsystem: provides pixels
- Display subsystem → VGA-to-HDMI IP: outputs video
- VGA-to-HDMI IP → HDMI monitor: sends HDMI
- Urbana FPGA → Top-level design: hosts design