# siubikyt/digital-logic-circuits architecture

> Architecture diagram of the GitHub repository siubikyt/digital-logic-circuits, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-09-27). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/siubikyt/digital-logic-circuits
- Repository: https://github.com/siubikyt/digital-logic-circuits

## Overview

This repository is a collection of digital logic circuit designs intended for use with Digital, a logic simulator. Its catalog covers arithmetic building blocks, ALUs, CPUs, selection and decoding circuits, and memory. The tree identifies these distinct circuit designs, but no source excerpts or README descriptions establish how they are composed or invoked. Accordingly, the graph groups the designs by function and omits speculative wiring between them or to the simulator.

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_arithmetic["Arithmetic"]
  node_half_adder["Half adder<br/>[Half adder.dig]"]
  node_full_adder["Full adder<br/>[Full adder.dig]"]
  node_half_subtractor["Half subtractor"]
  node_full_subtractor["Full subtractor"]
end

subgraph group_alus["ALUs"]
  node_alu_logic["8-bit ALU with logic gates"]
  node_alu_no_gates["8-bit ALU without logic gates"]
  node_alu_complex["Complex 8-bit ALU"]
end

subgraph group_cpus["CPUs"]
  node_cpu4["4-bit CPU<br/>[4 bit CPU.dig]"]
  node_cpu8["8-bit CPU<br/>[8 bit CPU.dig]"]
end

subgraph group_routing["Selection and decoding"]
  node_decoder3_8["3-to-8 decoder"]
  node_decoder4_16["4-to-16 decoder"]
  node_decoder5_32["5-to-32 decoder"]
  node_demux1_2["1x2 demultiplexer"]
  node_demux1_4["1x4 demultiplexer"]
  node_mux2_1["2x1 multiplexer"]
  node_mux4_1["4x1 multiplexer"]
end

subgraph group_memory["Memory"]
  node_ram8x8["8x8-bit RAM<br/>[8x8 bit RAM.dig]"]
  node_binary_cell["Binary cell<br/>[Binary cell.dig]"]
end

click node_half_adder "https://github.com/siubikyt/digital-logic-circuits/blob/main/Arithmetic/Addition/Half%20adder.dig"
click node_full_adder "https://github.com/siubikyt/digital-logic-circuits/blob/main/Arithmetic/Addition/Full%20adder.dig"
click node_half_subtractor "https://github.com/siubikyt/digital-logic-circuits/blob/main/Arithmetic/Subtraction/Half%20subtractor.dig"
click node_full_subtractor "https://github.com/siubikyt/digital-logic-circuits/blob/main/Arithmetic/Subtraction/Full%20subtractor.dig"
click node_alu_logic "https://github.com/siubikyt/digital-logic-circuits/blob/main/ALUs/8%20bit%20ALU%20logic%20gates.dig"
click node_alu_no_gates "https://github.com/siubikyt/digital-logic-circuits/blob/main/ALUs/8%20bit%20ALU%20no%20logic%20gates.dig"
click node_alu_complex "https://github.com/siubikyt/digital-logic-circuits/blob/main/ALUs/Complex%208%20bit%20ALU.dig"
click node_cpu4 "https://github.com/siubikyt/digital-logic-circuits/blob/main/CPUs/4%20bit%20CPU/4%20bit%20CPU.dig"
click node_cpu8 "https://github.com/siubikyt/digital-logic-circuits/blob/main/CPUs/8%20bit%20CPU/8%20bit%20CPU.dig"
click node_decoder3_8 "https://github.com/siubikyt/digital-logic-circuits/blob/main/Decoders/3%20to%208%20line%20decoder.dig"
click node_decoder4_16 "https://github.com/siubikyt/digital-logic-circuits/blob/main/Decoders/4%20to%2016%20line%20decoder.dig"
click node_decoder5_32 "https://github.com/siubikyt/digital-logic-circuits/blob/main/Decoders/5%20to%2032%20line%20decoder.dig"
click node_demux1_2 "https://github.com/siubikyt/digital-logic-circuits/blob/main/Demultiplexers/1x2%20demultiplexer.dig"
click node_demux1_4 "https://github.com/siubikyt/digital-logic-circuits/blob/main/Demultiplexers/1x4%20demultiplexer.dig"
click node_mux2_1 "https://github.com/siubikyt/digital-logic-circuits/blob/main/Multiplexers/2x1%20multiplexer.dig"
click node_mux4_1 "https://github.com/siubikyt/digital-logic-circuits/blob/main/Multiplexers/4x1%20multiplexer.dig"
click node_ram8x8 "https://github.com/siubikyt/digital-logic-circuits/blob/main/Memory/8x8%20bit%20RAM.dig"
click node_binary_cell "https://github.com/siubikyt/digital-logic-circuits/blob/main/Memory/Binary%20cell.dig"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_half_adder,node_full_adder,node_half_subtractor,node_full_subtractor toneBlue
class node_alu_logic,node_alu_no_gates,node_alu_complex toneAmber
class node_cpu4,node_cpu8 toneMint
class node_decoder3_8,node_decoder4_16,node_decoder5_32,node_demux1_2,node_demux1_4,node_mux2_1,node_mux4_1 toneRose
class node_ram8x8,node_binary_cell toneIndigo
```

## Components

### Arithmetic

- [Half adder](https://github.com/siubikyt/digital-logic-circuits/blob/main/Arithmetic/Addition/Half%20adder.dig): `Arithmetic/Addition/Half adder.dig`
- [Full adder](https://github.com/siubikyt/digital-logic-circuits/blob/main/Arithmetic/Addition/Full%20adder.dig): `Arithmetic/Addition/Full adder.dig`
- [Half subtractor](https://github.com/siubikyt/digital-logic-circuits/blob/main/Arithmetic/Subtraction/Half%20subtractor.dig): `Arithmetic/Subtraction/Half subtractor.dig`
- [Full subtractor](https://github.com/siubikyt/digital-logic-circuits/blob/main/Arithmetic/Subtraction/Full%20subtractor.dig): `Arithmetic/Subtraction/Full subtractor.dig`

### ALUs

- [8-bit ALU with logic gates](https://github.com/siubikyt/digital-logic-circuits/blob/main/ALUs/8%20bit%20ALU%20logic%20gates.dig): `ALUs/8 bit ALU logic gates.dig`
- [8-bit ALU without logic gates](https://github.com/siubikyt/digital-logic-circuits/blob/main/ALUs/8%20bit%20ALU%20no%20logic%20gates.dig): `ALUs/8 bit ALU no logic gates.dig`
- [Complex 8-bit ALU](https://github.com/siubikyt/digital-logic-circuits/blob/main/ALUs/Complex%208%20bit%20ALU.dig): `ALUs/Complex 8 bit ALU.dig`

### CPUs

- [4-bit CPU](https://github.com/siubikyt/digital-logic-circuits/blob/main/CPUs/4%20bit%20CPU/4%20bit%20CPU.dig): `CPUs/4 bit CPU/4 bit CPU.dig`
- [8-bit CPU](https://github.com/siubikyt/digital-logic-circuits/blob/main/CPUs/8%20bit%20CPU/8%20bit%20CPU.dig): `CPUs/8 bit CPU/8 bit CPU.dig`

### Selection and decoding

- [3-to-8 decoder](https://github.com/siubikyt/digital-logic-circuits/blob/main/Decoders/3%20to%208%20line%20decoder.dig): `Decoders/3 to 8 line decoder.dig`
- [4-to-16 decoder](https://github.com/siubikyt/digital-logic-circuits/blob/main/Decoders/4%20to%2016%20line%20decoder.dig): `Decoders/4 to 16 line decoder.dig`
- [5-to-32 decoder](https://github.com/siubikyt/digital-logic-circuits/blob/main/Decoders/5%20to%2032%20line%20decoder.dig): `Decoders/5 to 32 line decoder.dig`
- [1x2 demultiplexer](https://github.com/siubikyt/digital-logic-circuits/blob/main/Demultiplexers/1x2%20demultiplexer.dig): `Demultiplexers/1x2 demultiplexer.dig`
- [1x4 demultiplexer](https://github.com/siubikyt/digital-logic-circuits/blob/main/Demultiplexers/1x4%20demultiplexer.dig): `Demultiplexers/1x4 demultiplexer.dig`
- [2x1 multiplexer](https://github.com/siubikyt/digital-logic-circuits/blob/main/Multiplexers/2x1%20multiplexer.dig): `Multiplexers/2x1 multiplexer.dig`
- [4x1 multiplexer](https://github.com/siubikyt/digital-logic-circuits/blob/main/Multiplexers/4x1%20multiplexer.dig): `Multiplexers/4x1 multiplexer.dig`

### Memory

- [8x8-bit RAM](https://github.com/siubikyt/digital-logic-circuits/blob/main/Memory/8x8%20bit%20RAM.dig): `Memory/8x8 bit RAM.dig`
- [Binary cell](https://github.com/siubikyt/digital-logic-circuits/blob/main/Memory/Binary%20cell.dig): `Memory/Binary cell.dig`