How samiul000/vfpga-s3 works
VFPGA-S3 combines an ESP32-hosted software FPGA with an HDL-to-fabric workflow, an integrated RV32I soft CPU, and documented host-side simulation and educational ASIC-style physical design. The firmware entry point parses the embedded user design, builds and maps a netlist, loads the configuration into the fabric, and evaluates combinational or sequential outputs. The README documents additional host tools and Verilog emission. Some implementation paths for those capabilities were not sampled, so their nodes use exact enclosing directories and uncertain links are omitted.
Main entry points: src/main.cpp Firmware workflow · cli/main.cpp Host CLI · vfpga_core.cpp Fabric core · riscv_soc_demo.cpp Virtual SoC demo
Components 23
HDL workflow
- Firmware workflow
src/main.cpp - Embedded HDL
src/hdl/user_design.h - HDL lexer
src/hdl/lexer.cpp - HDL parser
src/hdl/parser.cpp - Netlist builder
src/hdl/netlist.cpp - LUT mapper
src/hdl/mapper.cpp - Verilog emitter
src/hdl/verilog_emit.cpp
Virtual fabric
- Fabric core
src/vfpga/vfpga_core.cpp - Logic and resources
src/vfpga - Routing fabric
src/vfpga/vfpga_pie.cpp - Execution modes
src/engine/execution_engine.cpp - Board profile
src/io/board_profile.cpp - GPIO bridge
src/io/gpio_bridge.cpp
RISC-V SoC
- RV32I CPU
src/riscv/riscv_cpu.cpp - CPU memory
src/riscv/riscv_memory.cpp - Virtual SoC demo
src/riscv/riscv_soc_demo.cpp - Built-in demos
src/demo_run.cpp
Host design tools
- Host CLI
tools/cli/main.cpp - Host simulator
host_test/simulator/sim.cpp - Testbench execution
host_test/testbench/tb_exec.cpp - Waveform output
host_test/waveform/vcd.cpp - Physical design
host_test/physical/physical_design.cpp
Other components
- Design author
Connections 28
- Design author → Embedded HDL: edits
- Embedded HDL → Firmware workflow: loaded by
src/main.cpp - Firmware workflow → HDL lexer: tokenizes
src/main.cpp - Firmware workflow → HDL parser: parses
src/main.cpp - Firmware workflow → Netlist builder: builds
src/main.cpp - Firmware workflow → LUT mapper: maps
src/main.cpp - Firmware workflow → Fabric core: loads and evaluates
src/main.cpp - Netlist builder → HDL parser: consumes AST
- LUT mapper → Netlist builder: maps netlist
- Fabric core → Routing fabric: uses routing
src/vfpga/vfpga_core.cpp - Fabric core → Logic and resources: evaluates fabric
src/vfpga/vfpga_core.cpp - Fabric core → Execution modes: evaluates with
- Firmware workflow → Board profile: detects board
src/main.cpp - Firmware workflow → GPIO bridge: initializes bridge
src/main.cpp - Firmware workflow → Built-in demos: runs demos
src/main.cpp - Built-in demos → Virtual SoC demo: runs demo
src/demo_run.cpp - Virtual SoC demo → RV32I CPU: uses CPU
src/riscv/riscv_soc_demo.cpp - Virtual SoC demo → Fabric core: uses fabric
src/riscv/riscv_soc_demo.cpp - RV32I CPU → CPU memory: uses memory
- Design author → Host CLI: runs commands
- Host CLI → HDL parser: loads HDL
- Host CLI → LUT mapper: maps design
- Host CLI → Host simulator: simulates design
- Host CLI → Testbench execution: verifies design
- Testbench execution → Host simulator: executes on
- Host CLI → Waveform output: exports waveform
- Host CLI → Physical design: runs physical flow
- Design author → Verilog emitter: can emit as