How samip08/asynchronous-fifo-based-axitoapb-bridge works
1. What this repo implements
This is a Verilog RTL design for an AXI-to-APB bridge. The bridge accepts AXI-style read/write transactions on one side, converts them into APB master cycles on the other side, and returns responses back to AXI. The design is organized as a set of small FSM-based blocks with clock-domain-crossing FIFOs in the middle.
2. Top-level composition
RTL/Top_module.v is the integration point. It ties together:
- axi_slave_fsm.v for AXI-side transaction capture and response handling
- async_fifo_core.v for CDC-safe buffering
- apb_master_fsm.v for APB bus sequencing
- apb_slave_mux.v for selecting one of many APB slaves
This is the main architectural boundary: AXI ingress, buffering/CDC, APB egress.
3. AXI-side request handling
axi_slave_fsm.v acts like a protocol adapter on the AXI side. It latches address/data when valid signals arrive, tolerates cases where address and data do not arrive in the same cycle, and keeps the AXI master stalled until the bridge is ready. It has separate handling for write and read requests, with state transitions designed to avoid overwriting latched values.
4. Two-way buffering across domains
async_fifo_core.v is the key CDC mechanism. The README indicates gray-coded read/write pointers, binary local pointers, and use of “next” pointer values to make empty/full decisions at the correct cycle. This prevents classic CDC failures like overwriting unread data or reading unpublished data. The design also uses asynchronous reset behavior and separate FIFO usage for request and response traffic.
5. Transaction flow for writes
For writes, the AXI-side FSM captures write address/data, pushes the request into the write-side FIFO, and asserts AXI ready/valid-style completion signals only when safe. The APB side later consumes the request, drives the APB bus, and returns a write response. The bridge also handles error cases by returning an APB/AXI error response rather than blindly completing the transfer.
6. Transaction flow for reads
For reads, the AXI-side FSM captures the read address and sends a read request through the FIFO. The APB master then performs the APB access, collects prdata, and sends the result back through the response path. The AXI-side FSM waits until the response FIFO produces data before completing the read.
7. APB master sequencing
apb_master_fsm.v is the protocol engine for APB. It drives the APB phases (psel, penable, pready handling) and distinguishes read versus write behavior. The README shows an intentional cycle delay to avoid consuming stale FIFO values and to let request/response handshakes settle cleanly before the state machine commits to the transaction type.
8. Error propagation and recovery
Error handling is built into the bridge path, not treated as an afterthought. The APB master can enter an error/response path when a peripheral signals failure, and the AXI side also detects local decode errors such as an invalid address region (address[31:28] == 4'h2 in the README). On error, the design clears outgoing flags and returns to idle cleanly.
9. APB slave selection
apb_slave_mux.v provides a 16-way APB slave fanout. The selected slave is determined by 4 address bits, and the mux forwards the chosen slave’s prdata, pready, and error signals back to the APB master. Only the addressed slave is effectively active, while the others remain deasserted.
10. Clocking and reset boundaries
The design explicitly treats the AXI and APB sides as decoupled domains, with the FIFO forming the safe boundary. The README also notes asynchronous reset usage, especially to avoid spurious behavior at power-up. This means the architecture is not just a simple bus adapter; it is a CDC-aware bridge.
11. Verification structure
The TB/ directory mirrors the RTL structure: there are testbenches for the top module, AXI slave FSM, APB master FSM, APB slave mux, async FIFO, and the overall AXI-bridge path. This suggests a modular verification strategy where each subsystem can be validated independently before end-to-end integration.
12. Supporting docs and artifacts
Waveforms/ contains waveform images that document key design issues and fixes, especially around FIFO pointer correctness and bridge sequencing. Extra_utilities/ includes reference material and a rom_memory.v helper, likely used for stimulus or memory modeling in verification.
13. How to draw the architecture
The clearest diagram is a left-to-right pipeline:
AXI master → AXI slave FSM → async FIFO(s) → APB master FSM → APB slave mux → APB peripherals, with the read response returning along the reverse path. The important architectural boundaries are the AXI/APB protocol boundary, the CDC FIFO boundary, and the APB slave-selection boundary.
Main entry points: axi_slave_fsm.v AXI FSM · apb_master_fsm.v APB FSM · async_fifo_core.v Req FIFO · Top_module.v Top module
Components 17
RTL
Synthesisable bridge logic
- Top module · Integrates AXI capture, CDC buffering, APB sequencing, and slave selection
RTL/Top_module.v - AXI FSM · Captures AXI requests, holds ready/valid handshakes, and returns read or write responses
RTL/axi_slave_fsm.v - Req FIFO · Asynchronous FIFO used to carry requests across the clock boundary
RTL/async_fifo_core.v - Resp FIFO · Asynchronous FIFO used to return APB results and responses back to the AXI side
RTL/async_fifo_core.v - APB FSM · Drives APB setup and access phases and formats read or write outcomes
RTL/apb_master_fsm.v - APB mux · Selects one of 16 APB slaves using address bits and forwards return signals
RTL/apb_slave_mux.v - Addr check · Local address-region check used to flag invalid or unsupported transactions
RTL/axi_slave_fsm.v
TB
Module-level and end-to-end verification
Docs
Reference material and waveform artifacts
- Waveforms · Captured traces documenting FIFO pointer and sequencing behavior
Waveforms - References · Supporting reading material and utility references for design and verification
Extra_utilities
Other components
- AXI master · Source of AXI read and write transactions
- APB slaves · Target APB peripherals behind the address-decoding mux
- Write path · Captures write address and data, forwards the request, and returns a write response
- Read path · Captures read address, forwards the request, and waits for returned data
- Reset boundary · Asynchronous reset behavior used to keep CDC and protocol state clean at startup
Connections 34
- AXI master → AXI FSM: AXI requests · Master issues read and write transactions into the bridge
- AXI FSM → Req FIFO: enqueue req · Captured requests are pushed toward the CDC boundary
- Req FIFO → APB FSM: dequeue req · APB side consumes requests after crossing clock domains
- APB FSM → APB mux: APB access · Master engine drives the selected APB transfer
- APB mux → APB slaves: select slave · Address bits choose one of the APB targets
- APB slaves → APB mux: prdata/pready/pslverr · Selected peripheral returns read data, ready, and error status
- APB FSM → Resp FIFO: enqueue resp · Completed APB result is buffered for return to AXI
- Resp FIFO → AXI FSM: dequeue resp · AXI side completes the original transaction after response arrival
- AXI FSM → Addr check: decode guard · Address region checks can short-circuit unsupported requests
- Addr check → Resp FIFO: error resp · Invalid addresses are converted into an error response path
- AXI FSM → Write path: write control · Write-side capture and completion logic
- AXI FSM → Read path: read control · Read-side capture and completion logic
- Write path → Req FIFO: write req · Write transactions are packaged and sent to the APB side
- Read path → Req FIFO: read req · Read transactions are packaged and sent to the APB side
- APB FSM → Write path: write resp · Write completion or failure is returned upstream
- APB FSM → Read path: read resp · Read data or failure is returned upstream
- Top module → AXI FSM: instantiates · Top-level integration includes the AXI-side FSM
- Top module → Req FIFO: instantiates · Top-level integration includes request buffering
- Top module → Resp FIFO: instantiates · Top-level integration includes response buffering
- Top module → APB FSM: instantiates · Top-level integration includes the APB master FSM
- Top module → APB mux: instantiates · Top-level integration includes APB slave selection
- Reset boundary → AXI FSM: reset · Async reset clears AXI-side state
- Reset boundary → Req FIFO: reset · Async reset clears FIFO pointers and flags
- Reset boundary → Resp FIFO: reset · Async reset clears FIFO pointers and flags
- Reset boundary → APB FSM: reset · Async reset clears APB-side state
- Top TB → Top module: verifies · Integration testbench exercises the full top module
- Bridge TB → Write path: verifies · System bench covers write-path behavior
- Bridge TB → Read path: verifies · System bench covers read-path behavior
- Module TBs → AXI FSM: verifies · Module benches isolate the AXI FSM
- Module TBs → APB FSM: verifies · Module benches isolate the APB master FSM
- Module TBs → Req FIFO: verifies · Module benches isolate FIFO correctness
- Module TBs → APB mux: verifies · Module benches isolate the APB slave mux
- Waveforms → Req FIFO: documents · Waveforms capture FIFO pointer and boundary behavior
- References → Module TBs: supports · Reference material and utilities support verification work