How s-steven-joshua/js-soc works
JS-SoC is a SystemVerilog RV32I single-cycle SoC. Its main workflow executes instructions on the CPU, routes load/store accesses through a bridge to normal memory or APB peripherals, and can write peripheral data back for CPU use. A separate boot path assembles incoming bytes into instructions and initializes IMEM. The README documents these flows and major capabilities; RTL variants differ, and the excerpts do not establish all module-level wiring, so the graph stays at documented subsystem boundaries where needed.
Main entry points: decoder_logic.sv APB Decoder · core.sv RV32I CPU · peripherial_ram.sv Peripheral RAM · datapath.sv Single-Cycle Datapath
Components 21
RV32I Processor
- RV32I CPU
RTL/SoC_V3/src/core.sv - Single-Cycle Datapath
RTL/SoC_V3/src/datapath.sv - Control Unit
RTL/SoC_V3/src/controller.sv - ALU
RTL/SoC_V3/src/alu.sv - Register File
RTL/SoC_V3/src/register_file.sv - Instruction Memory
RTL/SoC_V3/src/imem.sv
Memory Access
- Data Memory
RTL/SoC_V3/src/dmem.sv - Access Bridge
RTL/SoC_V3/src/bridge.sv - APB Master
RTL/SoC_V3/src/apb_master.sv - APB Decoder
RTL/SoC_V3/src/decoder_logic.sv
Peripherals
- UART
RTL/SoC_V3/src/uart_soc.sv - PWM
RTL/SoC_V3/src/pwm.sv - Timer
RTL/SoC_V3/src/timer.sv - I²C Peripheral
RTL/SoCV1/src/i2c_top.sv - Peripheral RAM
RTL/SoCV1/src/peripherial_ram.sv - Peripheral Write-Back
RTL/SoC_V3/src/datapath.sv
Instruction Boot
- Bootloader
RTL/SoC_V3/src/bootloader.sv
Control Word Tools
- PWM Word Generator
Java_files/pwm.java - Timer Word Generator
Java_files/timer_generation.java
Other components
- Program / Data Source
- External Boot Data
Connections 24
- Program / Data Source → RV32I CPU: provides program
README.md - RV32I CPU → Access Bridge: routes accesses
README.md - Access Bridge → Data Memory: selects normal memory
README.md - Access Bridge → APB Master: selects APB access
README.md - APB Master → APB Decoder: decodes address
README.md - APB Decoder → UART: selects peripheral
README.md - APB Decoder → PWM: selects peripheral
README.md - APB Decoder → Timer: selects peripheral
README.md - APB Decoder → I²C Peripheral: selects peripheral
README.md - UART → Peripheral RAM: writes peripheral data
README.md - PWM → Peripheral RAM: writes peripheral data
README.md - Timer → Peripheral RAM: writes peripheral data
README.md - I²C Peripheral → Peripheral RAM: writes peripheral data
README.md - Peripheral RAM → Peripheral Write-Back: supplies write-back data
README.md - Peripheral Write-Back → RV32I CPU: returns CPU data
README.md - External Boot Data → Bootloader: sends bytes
README.md - Bootloader → Instruction Memory: initializes instructions
README.md - Bootloader → RV32I CPU: holds during loading
README.md - Instruction Memory → RV32I CPU: provides instructions
README.md - Single-Cycle Datapath → Control Unit: uses control signals
- Single-Cycle Datapath → ALU: executes operations
- Single-Cycle Datapath → Register File: reads and writes
- PWM Word Generator → PWM: formats register value
- Timer Word Generator → Timer: formats control word