How rkycodes/anima works
ANIMA is an FPGA-oriented stereo I2S audio processor, currently implemented as a bypass path with diagnostics and control/clock-supervision logic; its DSP, wireless and display features remain planned. The principal documented audio workflow is receiver → coherent stereo-frame handoff → transmitter. The graph also preserves the current control/diagnostic modules and the Python preset/frame behavioral model. RTL integration details are not shown in the excerpts, so those internal connections are intentionally not inferred.
Main entry points: preset_manager.py Preset manager · anima_i2s_receiver.v I2S receiver · anima_rx_frame_queue.v RX frame queue · anima_frame_scheduler.v Frame scheduler
Components 25
Audio RTL
- I2S receiver
rtl/audio/anima_i2s_receiver.v - RX frame queue
rtl/audio/anima_rx_frame_queue.v - Frame scheduler
rtl/audio/anima_frame_scheduler.v - Bypass core
rtl/audio/anima_bypass_core.v - I2S transmitter
rtl/audio/anima_i2s_transmitter.v - Serial timing
rtl/audio/anima_serial_timing.v - Warm reset
rtl/audio/anima_warm_reset_controller.v - Audio watchdogs
rtl/audio/anima_audio_watchdogs.v - Audio diagnostics
rtl/audio/anima_audio_diagnostics.v
Control and supervision
- Control shell
rtl/audio/anima_bypass_control_shell.v - Clock supervisor
rtl/audio/anima_clock_supervisor.v - Button events
rtl/common/anima_button_event.v - Reset synchronizer
rtl/common/anima_reset_sync.v
Preset/frame model
- Preset lifecycle
sim/fpga_control_logic/preset.py - Preset manager
sim/fpga_control_logic/preset_manager.py - Audio frame model
sim/fpga_control_logic/audio_frame.py
Other components
- Stereo source
- I2S ADC
- I2S DAC
- Powered speakers
- Wireless controls
- ESP32
- FPGA UART/parser
- Planned DSP
- Planned VGA meters
Connections 13
- Stereo source → I2S ADC: audio to
README.md - I2S ADC → I2S receiver: audio to
README.md - I2S receiver → RX frame queue: frames to
README.md - RX frame queue → Frame scheduler: coherent frames
README.md - Frame scheduler → I2S transmitter: frames to
README.md - I2S transmitter → I2S DAC: audio to
README.md - I2S DAC → Powered speakers: audio to
README.md - Wireless controls → ESP32: controls
README.md - ESP32 → FPGA UART/parser: controls
README.md - FPGA UART/parser → Planned DSP: planned controls
README.md - Preset manager → Preset lifecycle: uses
sim/fpga_control_logic/preset_manager.py - Preset manager → Audio frame model: creates
sim/fpga_control_logic/preset_manager.py - Audio frame model → Preset lifecycle: holds snapshot
sim/fpga_control_logic/audio_frame.py