# riyatorane/chiplet-based-system-verilog architecture

> Architecture diagram of the GitHub repository riyatorane/chiplet-based-system-verilog, generated by GitDiagram from its file tree, README and a sample of source files (last updated 2026-11-12). It is an AI-made overview: check details against the source.

- Interactive diagram: https://gitdiagram.com/riyatorane/chiplet-based-system-verilog
- Repository: https://github.com/riyatorane/chiplet-based-system-verilog

## Overview

This Verilog design models a compute, memory, and I/O chiplet system connected by serialized die-to-die links, with a single-die bypass mode. The documented workload has the compute chiplet write and read values, add them, and send the result to the I/O chiplet; the memory chiplet provides packet-interface RAM. The link is described as serialization, wire delay, deserialization, and parity checking. Only the README was available as evidence, so the graph shows documented integration and link responsibilities, not an unverified packet topology or signal-level call flow.

Main entry points: [`chiplet_system.v`](https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/chiplet_system.v) (System Top), [`d2d_link.v`](https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/d2d_link.v) (D2D Link), [`compute_chiplet.v`](https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/compute_chiplet.v) (Compute Chiplet), [`memory_chiplet.v`](https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/memory_chiplet.v) (Memory Chiplet)

## Diagram (Mermaid)

```mermaid
flowchart TD

subgraph group_system["System Integration"]
  node_system_top["System Top<br/>[chiplet_system.v]"]
end

subgraph group_chiplets["Chiplet Workload"]
  node_compute["Compute Chiplet<br/>[compute_chiplet.v]"]
  node_memory[("Memory Chiplet<br/>[memory_chiplet.v]")]
  node_io["I/O Chiplet<br/>[io_chiplet.v]"]
end

subgraph group_link["D2D Link"]
  node_d2d_link["D2D Link<br/>[d2d_link.v]"]
  node_tx["Serializer<br/>[d2d_tx.v]"]
  node_phy["Wire Delay<br/>[d2d_phy.v]"]
  node_rx["Deserializer + Parity<br/>[d2d_rx.v]"]
end

node_system_top -->|"integrates"| node_compute
node_system_top -->|"integrates"| node_memory
node_system_top -->|"integrates"| node_io
node_system_top -->|"integrates"| node_d2d_link
node_d2d_link -->|"uses serialization"| node_tx
node_d2d_link -->|"uses wire delay"| node_phy
node_d2d_link -->|"uses deserialization"| node_rx

click node_system_top "https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/chiplet_system.v"
click node_compute "https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/compute_chiplet.v"
click node_memory "https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/memory_chiplet.v"
click node_io "https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/io_chiplet.v"
click node_d2d_link "https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/d2d_link.v"
click node_tx "https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/d2d_tx.v"
click node_phy "https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/d2d_phy.v"
click node_rx "https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/d2d_rx.v"

classDef toneNeutral fill:#f8fafc,stroke:#334155,stroke-width:1.5px,color:#0f172a
classDef toneBlue fill:#dbeafe,stroke:#2563eb,stroke-width:1.5px,color:#172554
classDef toneAmber fill:#fef3c7,stroke:#d97706,stroke-width:1.5px,color:#78350f
classDef toneMint fill:#dcfce7,stroke:#16a34a,stroke-width:1.5px,color:#14532d
classDef toneRose fill:#ffe4e6,stroke:#e11d48,stroke-width:1.5px,color:#881337
classDef toneIndigo fill:#e0e7ff,stroke:#4f46e5,stroke-width:1.5px,color:#312e81
classDef toneTeal fill:#ccfbf1,stroke:#0f766e,stroke-width:1.5px,color:#134e4a
class node_system_top toneBlue
class node_compute,node_memory,node_io toneAmber
class node_d2d_link,node_tx,node_phy,node_rx toneMint
```

## Components

### System Integration

- [System Top](https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/chiplet_system.v): `chiplet_system.v`

### Chiplet Workload

- [Compute Chiplet](https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/compute_chiplet.v): `compute_chiplet.v`
- [Memory Chiplet](https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/memory_chiplet.v): `memory_chiplet.v`
- [I/O Chiplet](https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/io_chiplet.v): `io_chiplet.v`

### D2D Link

- [D2D Link](https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/d2d_link.v): `d2d_link.v`
- [Serializer](https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/d2d_tx.v): `d2d_tx.v`
- [Wire Delay](https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/d2d_phy.v): `d2d_phy.v`
- [Deserializer + Parity](https://github.com/riyatorane/chiplet-based-system-verilog/blob/main/d2d_rx.v): `d2d_rx.v`

## Connections

- System Top → Compute Chiplet: integrates (evidence: `README.md`)
- System Top → Memory Chiplet: integrates (evidence: `README.md`)
- System Top → I/O Chiplet: integrates (evidence: `README.md`)
- System Top → D2D Link: integrates (evidence: `README.md`)
- D2D Link → Serializer: uses serialization (evidence: `README.md`)
- D2D Link → Wire Delay: uses wire delay (evidence: `README.md`)
- D2D Link → Deserializer + Parity: uses deserialization (evidence: `README.md`)