How raulbehl/100daysofrtl works
100DaysOfRTL is a hands-on RTL design and verification learning repository, organized as successive day-based examples rather than one integrated runtime. The README documents RTL design exercises, SystemVerilog testbench topics and examples, and formal verification exercises; the tree also shows later APB/UVM and RISC-V material. Since no source excerpts are available and the README is truncated, the graph captures these documented and tree-visible capability areas without inferring calls or execution flow between independent lessons.
Components 8
RTL Design
- RTL Exercises
day1
Testbench Learning
- Testbench Topics
day21 - Verification Examples
day40
Formal Verification
- Formal Exercises
day46
APB Verification
- APB UVM Examples
day61
RISC-V
- RISC-V Core
day80
Other components
- Learner
- Course Collection
README.md