How pynqpanthers/fractal-accelerator-rtl works
PYNQZOOM is an RTL fractal-rendering accelerator: the processing system configures a render and starts it, then programmable logic schedules work, computes pixels, tests uniform regions, stores the frame, and writes completed sixteenths to DDR. The graph reflects the README’s documented architecture and workflow; the RTL modules themselves were not sampled, so relationships are cited to that documentation rather than inferred from unseen calls. It shows the two design variants and their distinct precision/core-count tradeoff.
Main entry points: scheduler.sv Mariani-Silver scheduler · per_sixteenth_engine.sv Sixteenth engine · control_unit.sv Job control unit · top_level.sv Top-level control
Components 23
Render orchestration
- Top-level control
hdl/dual_core/top/top_level.sv - Sixteenth controller
hdl/dual_core/top/sixteenth_controller.sv - Sixteenth engine
hdl/dual_core/top/per_sixteenth_engine.sv - Job control unit
hdl/dual_core/control_unit/control_unit.sv - Job queue
hdl/dual_core/queues/job_queue.sv - Completion queue
hdl/dual_core/queues/complete_queue.sv
Work scheduling
- Mariani-Silver scheduler
hdl/dual_core/scheduler/scheduler.sv - Border pixel generator
hdl/dual_core/scheduler/border_pixel_generator.sv - Scheduler stack
hdl/dual_core/scheduler/scheduler_stack.sv - Border comparator
hdl/dual_core/comparator/comparator.sv
Pixel computation
- Core cluster
hdl/dual_core/control_unit/cluster/cluster.sv - Iterator core
hdl/dual_core/worker_core/core_top.sv
Frame storage and output
- Colour frame buffer
hdl/dual_core/memory/colour_bram.sv - Scheduler state memory
hdl/dual_core/memory/state_bram.sv - Tile metadata
hdl/dual_core/memory/tile_table.sv - DDR writeback
hdl/dual_core/memory/bram_to_dram.sv - AXI-HP master
hdl/dual_core/axi/axi_hp_master_wrap.sv
Design variants
- Dual-core variant
hdl/dual_core/top/top_level.sv - AXI write arbiter
hdl/dual_core/axi/axi_wr_arbiter.sv - Dual-precision variant
hdl/dual_precision/top/top_level.sv - Wide multiply manager
hdl/dual_precision/worker_core/multiply_manager.sv
Other components
- Processing system
- DDR memory
Connections 21
- Processing system → Top-level control: configures and starts
README.md - Top-level control → Sixteenth controller: sequences frames
README.md - Sixteenth controller → Sixteenth engine: runs sixteenths
README.md - Sixteenth engine → Mariani-Silver scheduler: schedules pixels
README.md - Mariani-Silver scheduler → Border pixel generator: requests border pixels
README.md - Mariani-Silver scheduler → Scheduler stack: manages quad-tree
README.md - Mariani-Silver scheduler → Job control unit: dispatches jobs
README.md - Job control unit → Job queue: queues jobs
README.md - Job control unit → Core cluster: arbitrates work
README.md - Core cluster → Iterator core: assigns pixels
README.md - Iterator core → Completion queue: returns results
README.md - Completion queue → Border comparator: feeds border results
README.md - Border comparator → Mariani-Silver scheduler: reports uniformity
README.md - Sixteenth engine → Colour frame buffer: stores frame pixels
README.md - Mariani-Silver scheduler → Scheduler state memory: uses scheduler state
README.md - Mariani-Silver scheduler → Tile metadata: uses tile metadata
README.md - Sixteenth engine → DDR writeback: streams completed frame
README.md - DDR writeback → AXI-HP master: writes over AXI-HP
README.md - AXI-HP master → DDR memory: writes frame data
README.md - Dual-core variant → AXI write arbiter: merges engine writes
README.md - Dual-precision variant → Wide multiply manager: supports wide mode
README.md