poornachandra-29/coa

How poornachandra-29/coa works

This repository implements a five-stage pipelined CPU for a small MIPS-like ISA, with assembler and reference-model tools. The principal workflow is instruction fetch, decode, execute, memory access, and write-back; hazard detection, forwarding, and pipeline registers preserve correctness across stages. The datapath relationships below are based on the architecture depicted in tools/make_diagram.py; RTL source was not sampled, so implementation details beyond that diagram are not asserted.

Main entry points: pipeline_id_ex.v ID/EX register · pipeline_if_id.v IF/ID register · pipeline_mem_wb.v MEM/WB register · pipeline_ex_mem.v EX/MEM register

Components 20

Fetch and Decode

Program counter pipeline_cpu/src/program_counter.v
Instruction memory pipeline_cpu/src/instruction_memory.v
IF/ID register pipeline_cpu/src/pipeline_if_id.v
Control unit pipeline_cpu/src/control_unit.v
Register file pipeline_cpu/src/register_file.v
Sign extension pipeline_cpu/src/sign_extend.v

Execute and Control

Hazard detection pipeline_cpu/src/hazard_detection_unit.v
ID/EX register pipeline_cpu/src/pipeline_id_ex.v
Forwarding unit pipeline_cpu/src/forwarding_unit.v
ALU control pipeline_cpu/src/alu_control.v
ALU pipeline_cpu/src/alu.v
2-way muxes pipeline_cpu/src/mux2.v
3-way muxes pipeline_cpu/src/mux3.v

Memory and Writeback

EX/MEM register pipeline_cpu/src/pipeline_ex_mem.v
Data memory pipeline_cpu/src/data_memory.v
MEM/WB register pipeline_cpu/src/pipeline_mem_wb.v

Program Tools

Assembler pipeline_cpu/tools/assemble.py
ISA reference model pipeline_cpu/tools/golden.py

Other components

Program author
Program image pipeline_cpu/programs

Connections 29

Program author → Assembler: writes source pipeline_cpu/tools/assemble.py
Assembler → Program image: emits image pipeline_cpu/tools/assemble.py
Program counter → Instruction memory: addresses
Instruction memory → IF/ID register: passes instruction
IF/ID register → Control unit: supplies instruction
IF/ID register → Register file: selects registers
IF/ID register → Sign extension: supplies immediate
Control unit → ID/EX register: passes controls
Register file → ID/EX register: passes operands
Sign extension → ID/EX register: passes immediate
Hazard detection → Program counter: stalls fetch
Hazard detection → IF/ID register: holds or flushes
Hazard detection → ID/EX register: inserts bubble
ID/EX register → ALU control: supplies operation
ID/EX register → Forwarding unit: supplies register IDs
Forwarding unit → 3-way muxes: selects operands
ID/EX register → 2-way muxes: supplies immediate
3-way muxes → ALU: provides forwarded inputs
2-way muxes → ALU: selects operand B
ALU control → ALU: controls operation
ALU → EX/MEM register: passes result
EX/MEM register → Data memory: accesses memory
EX/MEM register → MEM/WB register: passes ALU result
Data memory → MEM/WB register: passes read data
MEM/WB register → 2-way muxes: selects writeback data
MEM/WB register → Register file: writes registers
EX/MEM register → Forwarding unit: provides result
MEM/WB register → Forwarding unit: provides writeback data
ISA reference model → Program image: reads image pipeline_cpu/tools/golden.py

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